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92 //
93 // File Name: mhal_CEC.c
94 // Description: For CEC functions.
95 ////////////////////////////////////////////////////////////////////////////////
96
97
98 #define _MHAL_CEC_C_
99
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105 #include "MsCommon.h"
106 #include "cec_hwreg_utility2.h"
107 #include "cec_Analog_Reg.h"
108 #include "MsOS.h"
109 #include "apiCEC.h"
110 #include "MsIRQ.h"
111 #include "mhal_CEC.h"
112 #include "asmCPU.h"
113
114 extern MS_VIRT CEC_RIU_BASE;
115 extern InterruptNum gCECIRQ;
116 extern MS_U8 g_u8CecVendorID[3];
117 extern MS_U8 g_u8RetryCnt;
118
119 #define CEC_DPUTSTR(str) //printf(str)
120 #define CEC_DPRINTF(str, x) //printf(str, x)
121
122 #define PM_REG_WRITE MDrv_WriteByte
123 #define PM_REG_READ MDrv_ReadByte
124
125
126 #define MST_XTAL_CLOCK_HZ (12000000UL) /* Temp define */
127
128 #define _NOP_ MAsm_CPU_Nop();
129
mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)130 void mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)
131 {
132
133 }
134
mhal_CEC_init_riu_base(MS_VIRT u32riu_base,MS_VIRT u32PMriu_base)135 void mhal_CEC_init_riu_base(MS_VIRT u32riu_base, MS_VIRT u32PMriu_base)
136 {
137 CEC_RIU_BASE = u32PMriu_base;
138 }
139
140
mhal_CEC_HeaderSwap(MS_U8 value)141 MS_U8 mhal_CEC_HeaderSwap(MS_U8 value)
142 {
143 return(((value&0x0f)<<4)+((value&0xf0)>>4));
144 }
145
mhal_CEC_SendFrame(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)146 MS_U8 mhal_CEC_SendFrame(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
147 {
148 MS_U8 i, cnt, *ptr, res;
149 MS_U8 u8waitcnt;
150
151 // clear CEC TX INT status
152 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
153 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
154 PM_REG_WRITE( L_BK_CEC(0x18), header );
155 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
156
157 CEC_DPUTSTR("\r\n/******** CEC Tx **********/\r\n");
158 CEC_DPRINTF("CEC Tx FIFO= 0x%x", (MS_U8)header);
159 CEC_DPRINTF(" 0x%x", (MS_U8)opcode);
160
161 if(len > 0)
162 {
163 ptr=operand;
164 for(i=0;i<len;i++)
165 {
166 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
167 CEC_DPRINTF(" 0x%x", *(operand+i));
168 }
169 CEC_DPUTSTR("\r\n/**************************/\r\n");
170 }
171
172 if((PM_REG_READ(L_BK_CEC(0x05))== 1) && (PM_REG_READ(H_BK_CEC(0x05))== 0)) // CEC idle
173 {
174 CEC_DPUTSTR("*** CEC idle!!! ***\n");
175
176 // CEC transmit length
177 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
178 if((opcode==0x00)&&(len==0))
179 {
180 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
181 u8waitcnt = 5;
182 }
183 else
184 {
185 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
186 u8waitcnt = 4 * (len+2);
187 }
188
189 //The total time,
190 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
191 // = 28.5 ms (1), or 52.5 ms (2), ....
192 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
193 // = 28.5 + 35.2 * 3 = 133.6 ms
194
195 cnt=0;
196 MsOS_DelayTask(20);
197
198 do
199 {
200 MsOS_DelayTask(10);
201 if(cnt++>=u8waitcnt)
202 break;
203 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
204 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
205
206 if(cnt>=u8waitcnt)
207 res |= E_CEC_SYSTEM_BUSY;
208
209 // clear CEC TX INT status
210 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
211 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
212 }
213 else
214 {
215 CEC_DPUTSTR("*** system busy!!! ***\n");
216
217 res = E_CEC_SYSTEM_BUSY;
218 }
219
220 return res;
221 }
222
mhal_CEC_SendFramex(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)223 MS_U8 mhal_CEC_SendFramex(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
224 {
225 MS_U8 i, cnt, *ptr, res;
226 MS_U8 u8waitcnt;
227 volatile MS_U16 k, m;
228 // clear CEC TX INT status
229 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
230 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
231 PM_REG_WRITE( L_BK_CEC(0x18), header );
232 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
233
234 CEC_DPUTSTR("\r\n/******** CEC Tx **********/\r\n");
235 CEC_DPRINTF("CEC Tx FIFO= 0x%x", (MS_U8)header);
236 CEC_DPRINTF(" 0x%x", (MS_U8)opcode);
237
238 if(len > 0)
239 {
240 ptr=operand;
241 for(i=0;i<len;i++)
242 {
243 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
244 CEC_DPRINTF(" 0x%x", *(operand+i));
245 }
246 CEC_DPUTSTR("\r\n/**************************/\r\n");
247 }
248
249 if((PM_REG_READ(L_BK_CEC(0x05))== 1) && (PM_REG_READ(H_BK_CEC(0x05))== 0)) // CEC idle
250 {
251 CEC_DPUTSTR("*** CEC idle!!! ***\n");
252
253 // CEC transmit length
254 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
255 if((opcode==0x00)&&(len==0))
256 {
257 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
258 u8waitcnt = 5;
259 }
260 else
261 {
262 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
263 u8waitcnt = 30;
264 }
265
266 //The total time,
267 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
268 // = 28.5 ms (1), or 52.5 ms (2), ....
269 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
270 // = 28.5 + 35.2 * 3 = 133.6 ms
271
272 cnt=0;
273 //MsOS_DelayTask(20);
274 for(k = 0; k< 20000; k++)
275 {
276 _NOP_
277 _NOP_
278 _NOP_
279 }
280
281 do
282 {
283 //MsOS_DelayTask(10);
284 for(k = 0; k< 20000; k++)
285 {
286 for(m=0;m<50;m++)
287 {
288 _NOP_
289 _NOP_
290 _NOP_
291 _NOP_
292 _NOP_
293 }
294 }
295 if(cnt++>=u8waitcnt)
296 break;
297 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
298
299 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
300
301 if(cnt>=u8waitcnt)
302 res |= E_CEC_SYSTEM_BUSY;
303
304 // clear CEC TX INT status
305 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
306 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
307 }
308 else
309 {
310 CEC_DPUTSTR("*** system busy!!! ***\n");
311
312 res = E_CEC_SYSTEM_BUSY;
313 }
314
315 return res;
316 }
317
mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)318 void mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)
319 {
320 PM_REG_WRITE(L_BK_CEC(0x02), (PM_REG_READ(L_BK_CEC(0x02)) & 0x0F) |(mylogicaladdress<<4));
321 }
322
mhal_CEC_INTEn(MS_BOOL bflag)323 void mhal_CEC_INTEn(MS_BOOL bflag)
324 {
325 if(bflag) // unmask
326 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E); //REG_HDMI_INT_MASK
327
328 else // Mask CEC interrupt
329 #if ENABLE_CEC_MULTIPLE
330 PM_REG_WRITE(L_BK_CEC(0x13), 0x7F); //REG_HDMI_INT_MASK
331 #else
332 PM_REG_WRITE(L_BK_CEC(0x13), 0x1F); //REG_HDMI_INT_MASK
333 #endif
334 }
335
336
mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz)337 void mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz)
338 {
339 MS_U16 reg_val0, reg_val1;
340
341 #if ENABLE_CEC_INT
342
343 // CEC irq clear
344 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F);
345 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
346 // CEC irq mask control -only enable CEC rx irq
347 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E);
348 // CEC interrupt mask for PM/normal function
349 PM_REG_WRITE(L_BK_CEC(0x30), 0x08); // 11_30[3] = 1 Interrupt clear type select (Level), clear by itself
350
351 gCECIRQ = E_INT_IRQ_CEC; // IRQ55
352 #endif
353
354 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
355 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
356 PM_REG_WRITE(H_BK_CEC(0x00),0x10|RETRY_CNT); // retry times
357 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
358 PM_REG_WRITE(H_BK_CEC(0x01),(BusFreeTime<<4)|(ReTxInterval)); // CNT1=ReTxInterval; CNT2=BusFreeTime;
359 PM_REG_WRITE(L_BK_CEC(0x02),(E_LA_TV<<4)|(FrameInterval)); // CNT3=FrameInterval; [7:4]=logical address: TV
360 #if ENABLE_CEC_MULTIPLE
361 PM_REG_WRITE(L_BK_CEC(0x30),PM_REG_READ(L_BK_CEC(0x30))|BIT(0)); // enable CEC multiple function
362 #endif
363 reg_val0=(MST_XTAL_CLOCK_HZ%100000l)*0.00016+0.5;
364 PM_REG_WRITE(H_BK_CEC(0x02),(MST_XTAL_CLOCK_HZ/100000l)); // CEC time unit by Xtal(integer)
365 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
366 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
367
368 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF); // clear CEC status
369 }
370
mhal_CEC_IsMessageReceived(void)371 MS_BOOL mhal_CEC_IsMessageReceived(void)
372 {
373 return (PM_REG_READ(H_BK_CEC(0x11))& 0x01 ? TRUE : FALSE);
374 }
375
mhal_CEC_ReceivedMessageLen(void)376 MS_U8 mhal_CEC_ReceivedMessageLen(void)
377 {
378 return ((PM_REG_READ(L_BK_CEC(0x04)) & 0x1F) + 1);
379 }
380
mhal_CEC_GetMessageByte(MS_U8 idx)381 MS_U8 mhal_CEC_GetMessageByte(MS_U8 idx)
382 {
383 return (PM_REG_READ(L_BK_CEC(0x20) + idx));
384 }
385
mhal_CEC_ClearRxStatus(void)386 void mhal_CEC_ClearRxStatus(void)
387 {
388 // clear RX INT status
389 PM_REG_WRITE(H_BK_CEC(0x12), 0x11);
390 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
391 // clear RX NACK status
392 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF);
393 }
394
395 /***************************************************************************************/
396 /// config cec wake up
397 /***************************************************************************************/
398
mhal_CEC_ConfigWakeUp(void)399 void mhal_CEC_ConfigWakeUp(void)
400 {
401 MS_U16 reg_val0, reg_val1;
402 CEC_DPUTSTR("\r\n Here do the PM config cec wakeup \r\n");
403
404 //XBYTE[0x250C] &= ~BIT0;
405 MDrv_WriteByte( REG_DVI_ATOP_06_L, MDrv_ReadByte(REG_DVI_ATOP_06_L) &(~ BIT(0)));
406
407 //(1) enable chiptop clk_mcu & clk_pram
408 #if 0
409 XBYTE[0x0E00] = 0x03;
410 //enable PM_Sleep's clk_mcu and _pram
411 Drv_WriteByte(L_BK_PMSLP(0x00), 0x03);
412 XBYTE[0x0E01] = 0x0F;
413 //0x0C; Ken 20080916 for calibration to 1Mz
414 MDrv_WriteByte(H_BK_PMSLP(0x00), 0x0F);
415 #endif
416
417
418 //(2) HDMI CEC settings
419 PM_REG_WRITE(H_BK_CEC(0x00),0x10|g_u8RetryCnt); // retry times
420 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
421 PM_REG_WRITE(H_BK_CEC(0x01),0x63); // CNT1=3; CNT2 = 6;
422 PM_REG_WRITE(L_BK_CEC(0x02),0x07); // CNT3=7; logical address: TV
423
424 reg_val0=(MST_XTAL_CLOCK_HZ%100000l)*0.00016+0.5;
425 PM_REG_WRITE(H_BK_CEC(0x02),(MST_XTAL_CLOCK_HZ/100000l)); // CEC time unit by Xtal(integer)
426
427 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
428 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
429
430
431 //(3) PM Sleep: wakeup enable sources
432 //PM_REG_WRITE(L_BK_PMMCU(0x00),0x01); // reg_cec_enw
433
434
435 //(4) PM CEC power down controller settings
436 // Mask CEC interrupt in standby mode
437 PM_REG_WRITE(L_BK_CEC(0x13),0xFF);
438 // select power down SW CEC controller
439 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
440 PM_REG_WRITE(L_BK_CEC(0x01),0x00); // [5]:CEC clock no gate; [7]: Disable CEC controller
441 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
442 #if 0//ENABLE_SW_CEC_WAKEUP
443 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
444 #else
445 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))|(BIT(4))); // [4]: sleep mode;
446 #endif
447
448
449 //(5) PM CEC wakeup opcode settings
450 // OPCODE0: 0x04(Image view on)
451 // OPCODE1: 0x0D(Text view on)
452 // OPCODE2: 0x44 0x40(Power)
453 // 0x44 0x6D(Power ON Function)
454 // OPCODE3: N/A
455 // OPCODE4: 0x82(Active source) length = 2
456 PM_REG_WRITE(L_BK_CEC(0x07), 0x37); // Enable OP0~2 and OP4
457 PM_REG_WRITE(H_BK_CEC(0x07), 0x24); // Eanble OPCODE2's operand
458
459 PM_REG_WRITE(L_BK_CEC(0x08), E_MSG_OTP_IMAGE_VIEW_ON); // OPCODE0: Image View On
460 PM_REG_WRITE(H_BK_CEC(0x08), E_MSG_OTP_TEXT_VIEW_ON); // OPCODE1: Text View ON
461
462 PM_REG_WRITE(L_BK_CEC(0x09), E_MSG_UI_PRESS); // OPCODE2: E_MSG_UI_PRESS
463 PM_REG_WRITE(H_BK_CEC(0x0B), E_MSG_UI_POWER); // OPCODE2 operand: Power
464 PM_REG_WRITE(L_BK_CEC(0x0C), E_MSG_UI_POWER_ON_FUN); // OPCODE2 operand: Power ON
465
466 PM_REG_WRITE(L_BK_CEC(0x0A), E_MSG_ACTIVE_SOURCE); // OPCODE4: Active source
467
468 // [2:0]: CEC version 1.4; [7]: OP4 is broadcast message
469 PM_REG_WRITE(H_BK_CEC(0x0D), 0x80 | HDMI_CEC_VERSION);
470
471
472 //(6) Device(TV) Vendor ID for customer (Big Endian)
473 // It depends end-customer's vendor ID
474 MS_DEBUG_MSG(printf("!!!!!!!!!!!!!!!!!!!Change this Vendor ID according to customer!!!!!!!!!!!!!!!!\n"));
475 PM_REG_WRITE(L_BK_CEC(0x0F), g_u8CecVendorID[0]); // Device Vendor ID
476 PM_REG_WRITE(H_BK_CEC(0x0F), g_u8CecVendorID[1]); // Device Vendor ID
477 PM_REG_WRITE(L_BK_CEC(0x10), g_u8CecVendorID[2]); // Device Vendor ID
478
479 // [2:0]: Feature abort reason - "Not in correct mode to respond"
480 PM_REG_WRITE(H_BK_CEC(0x10), E_MSG_AR_CANNOTRESPOND );
481
482 //(7) Device Physical address: default is 0x00 0x00 0x00
483 PM_REG_WRITE(L_BK_CEC(0x0E), 0x00); // Physical address 0.0
484 PM_REG_WRITE(H_BK_CEC(0x0E), 0x00); // Physical address 0.0
485 PM_REG_WRITE(H_BK_CEC(0x14), 0x00); // Device type: TV
486
487 //(8) Clear CEC status
488 PM_REG_WRITE(L_BK_CEC(0x11), 0x7F); // Clear CEC wakeup status
489 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F); // Clear RX/TX/RF/LA/NACK status status
490 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
491 }
492
mhal_CEC_Enabled(MS_BOOL bEnableFlag)493 void mhal_CEC_Enabled(MS_BOOL bEnableFlag)
494 {
495 if(bEnableFlag)
496 PM_REG_WRITE(L_BK_CEC(0x01),0x80); //Enable PM CEC controller
497 else
498 PM_REG_WRITE(L_BK_CEC(0x01),0x00); //Disable PM CEC controller
499 }
500
mhal_CEC_TxStatus(void)501 MS_U8 mhal_CEC_TxStatus(void)
502 {
503 return (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
504 }
505
mhal_CEC_Device_Is_Tx(void)506 MS_BOOL mhal_CEC_Device_Is_Tx(void)
507 {
508 return CEC_DEVICE_IS_SOURCE;
509 }
510