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Searched refs:REG_DVI_ATOP2_32_L (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c1337 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(12), BMASK(13:12)); // Port D in Hal_HDMI_init()
3649 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_HIGH << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3654 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_MEDIUM << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3659 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3664 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c1337 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(12), BMASK(13:12)); // Port D in Hal_HDMI_init()
3649 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_HIGH << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3654 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_MEDIUM << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3659 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3664 W2BYTEMSK(REG_DVI_ATOP2_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2789 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
2794 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
2799 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
2804 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c486 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
624 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
701 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c486 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
624 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
701 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3526 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
3531 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
3536 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
3541 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5148 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5153 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5158 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5163 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5248 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5253 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5258 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5263 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5286 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5291 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5296 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5301 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5248 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5253 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5258 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5263 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5259 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5264 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5269 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5274 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5286 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5291 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5296 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5301 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c5851 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5856 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5861 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5866 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c5854 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5859 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5864 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5869 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5557 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5562 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5567 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5572 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c5857 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5862 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5867 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5872 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5557 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5562 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5567 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5572 W2BYTEMSK(REG_DVI_ATOP2_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h830 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h830 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) macro

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