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Searched refs:REG_DVI_ATOP1_32_L (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c1336 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(12), BMASK(13:12)); // Port B in Hal_HDMI_init()
3533 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_HIGH << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3538 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_MEDIUM << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3543 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3548 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c1336 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(12), BMASK(13:12)); // Port B in Hal_HDMI_init()
3533 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_HIGH << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3538 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_MEDIUM << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3543 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
3548 W2BYTEMSK(REG_DVI_ATOP1_32_L, (HDMI_HF_SETTING_VALUE_LOW << 8), BMASK(9:8)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2707 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
2712 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
2717 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
2722 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c430 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
565 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
677 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c430 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
565 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
677 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3444 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
3449 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
3454 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
3459 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5066 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5071 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5076 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5081 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5166 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5171 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5176 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5181 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5204 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5209 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5214 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5219 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5166 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5171 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5176 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5181 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5177 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5182 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5187 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5192 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5204 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5209 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5214 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5219 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c5769 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5774 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5779 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5784 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c5772 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5777 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5782 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5787 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5475 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5480 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5485 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5490 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c5775 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5780 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5785 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5790 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5475 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5480 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8)); in Hal_DVI_HF_adjust()
5485 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
5490 W2BYTEMSK(REG_DVI_ATOP1_32_L, 0, BMASK(9:8)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h798 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h798 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h790 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h790 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h790 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h790 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h790 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h790 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) macro

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