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Searched refs:REG_DTA_CTRL (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBT/
H A DINTERN_DVBT.h260 #define REG_DTA_CTRL 0x20CD macro
267 #define REG_DTA_CTRL 0x2F1D macro
274 #define _REG_DRQ REG_DTA_CTRL
276 #define _REG_ERR REG_DTA_CTRL
H A DINTERN_DVBT.c352 status &= INTERN_DVBT_ReadReg(REG_DTA_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
353 status &= INTERN_DVBT_WriteReg(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
364 status &= INTERN_DVBT_ReadReg(REG_DTA_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBC/
H A DINTERN_DVBC_Private.h246 #define REG_DTA_CTRL 0x20CD macro
252 #define _REG_DRQ REG_DTA_CTRL
254 #define _REG_ERR REG_DTA_CTRL
H A DINTERN_DVBC.c311 status &= INTERN_DVBC_ReadReg(REG_DTA_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
312 status &= INTERN_DVBC_WriteReg(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
317 status &= INTERN_DVBC_ReadReg(REG_DTA_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_common.h109 #define REG_DTA_CTRL MBRegBase + 0x1D macro
115 #define _REG_DRQ REG_DTA_CTRL
117 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_common.h120 #define REG_DTA_CTRL MBRegBase + 0x1D macro
126 #define _REG_DRQ REG_DTA_CTRL
128 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_common.h120 #define REG_DTA_CTRL MBRegBase + 0x1D macro
126 #define _REG_DRQ REG_DTA_CTRL
128 #define _REG_ERR REG_DTA_CTRL
H A DhalDMD_INTERN_DVBC.c458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
459 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
464 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_common.h121 #define REG_DTA_CTRL MBRegBase + 0x1D macro
127 #define _REG_DRQ REG_DTA_CTRL
129 #define _REG_ERR REG_DTA_CTRL
H A DhalDMD_INTERN_DVBC.c459 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
460 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
465 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_common.h120 #define REG_DTA_CTRL MBRegBase + 0x1D macro
126 #define _REG_DRQ REG_DTA_CTRL
128 #define _REG_ERR REG_DTA_CTRL
H A DhalDMD_INTERN_DVBC.c458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
459 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
464 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_common.h120 #define REG_DTA_CTRL MBRegBase + 0x1D macro
126 #define _REG_DRQ REG_DTA_CTRL
128 #define _REG_ERR REG_DTA_CTRL
H A DhalDMD_INTERN_DVBC.c458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
459 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
464 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_common.h120 #define REG_DTA_CTRL MBRegBase + 0x1D macro
126 #define _REG_DRQ REG_DTA_CTRL
128 #define _REG_ERR REG_DTA_CTRL
H A DhalDMD_INTERN_DVBC.c458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
459 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
464 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_common.h110 #define REG_DTA_CTRL MBRegBase + 0x1D macro
116 #define _REG_DRQ REG_DTA_CTRL
118 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_common.h128 #define REG_DTA_CTRL MBRegBase + 0x1D macro
134 #define _REG_DRQ REG_DTA_CTRL
136 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_common.h110 #define REG_DTA_CTRL MBRegBase + 0x1D macro
116 #define _REG_DRQ REG_DTA_CTRL
118 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_common.h120 #define REG_DTA_CTRL MBRegBase + 0x1D macro
126 #define _REG_DRQ REG_DTA_CTRL
128 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_common.h121 #define REG_DTA_CTRL MBRegBase + 0x1D macro
127 #define _REG_DRQ REG_DTA_CTRL
129 #define _REG_ERR REG_DTA_CTRL
H A DhalDMD_INTERN_DVBC.c459 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
460 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
465 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_common.h118 #define REG_DTA_CTRL MBRegBase + 0x1D macro
124 #define _REG_DRQ REG_DTA_CTRL
126 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_common.h117 #define REG_DTA_CTRL MBRegBase + 0x1D macro
123 #define _REG_DRQ REG_DTA_CTRL
125 #define _REG_ERR REG_DTA_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_common.h121 #define REG_DTA_CTRL MBRegBase + 0x1D macro
127 #define _REG_DRQ REG_DTA_CTRL
129 #define _REG_ERR REG_DTA_CTRL

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