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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _INTERN_DVBT_H_ 96 #define _INTERN_DVBT_H_ 97 98 #ifdef _INTERN_DVBT_C_ 99 #define EXTSEL 100 #else 101 #define EXTSEL extern 102 #endif 103 104 105 //-------------------------------------------------------------------- 106 107 // #define DEMOD_DYNAMIC_SLAVE_ID_1 0x32 108 // #define DEMOD_DYNAMIC_SLAVE_ID_2 0x72 109 // #define DEMOD_DYNAMIC_SLAVE_ID_3 0xB2 110 // #define DEMOD_DYNAMIC_SLAVE_ID_4 0xF2 111 112 #define DEMOD_ADDR_H 0x00 113 #define DEMOD_ADDR_L 0x01 114 #define DEMOD_WRITE_REG 0x02 115 #define DEMOD_WRITE_REG_EX 0x03 116 #define DEMOD_READ_REG 0x04 117 #define DEMOD_RAM_CONTROL 0x05 118 119 // #define INTERN_DVBT_IIC_CONTROL 0x8400 120 // #define INTERN_DVBT_IIC_SCL_CLK 0x8401 121 // #define INTERN_DVBT_IIC_READ_DATA 0x8402 122 // #define INTERN_DVBT_IIC_STATUS 0x8403 123 // #define INTERN_DVBT_IIC_WRITE_DATA 0x8404 124 125 // #define COFDM_DEM_I2C_ID DEMOD_DYNAMIC_SLAVE_ID_1 126 // #define COFDM_DEM_I2C_ID_2 DEMOD_DYNAMIC_SLAVE_ID_2 127 // #define COFDM_DEM_I2C_ID_3 DEMOD_DYNAMIC_SLAVE_ID_3 128 // #define COFDM_DEM_I2C_ID_4 DEMOD_DYNAMIC_SLAVE_ID_4 129 130 // #define INTERN_DVBT_REG_INVERSION 0x8024 131 #define BOOL BOOLEAN 132 133 #if DTV_SCAN_AUTO_FINE_TUNE_ENABLE 134 //INTERN_DVBT_ Capture Range fix to 500K 135 #define DEMOD_CAPTURE_RANGE_500_K 500 136 #define DEMOD_CAPTURE_RANGE_SIZE DEMOD_CAPTURE_RANGE_500_K 137 #endif 138 139 140 typedef enum 141 { 142 COFDM_FEC_LOCK, 143 COFDM_PSYNC_LOCK, 144 COFDM_TPS_LOCK, 145 COFDM_DCR_LOCK, 146 COFDM_AGC_LOCK, 147 COFDM_MODE_DET, 148 149 } COFDM_LOCK_STATUS; 150 151 //-------------------------------------------------------------------- 152 typedef enum 153 { 154 E_SYS_UNKOWN = -1, 155 E_SYS_DVBT, 156 E_SYS_DVBC, 157 E_SYS_ATSC, 158 E_SYS_VIF, 159 160 E_SYS_NUM 161 }E_SYSTEM; 162 163 typedef enum 164 { 165 CMD_SYSTEM_INIT = 0, 166 CMD_DAC_CALI, 167 CMD_DVBT_CONFIG, 168 CMD_DVBC_CONFIG, 169 CMD_VIF_CTRL, 170 CMD_FSM_CTRL, 171 CMD_INDIR_RREG, 172 CMD_INDIR_WREG, 173 CMD_GET_INFO, 174 CMD_TS_CTRL, 175 CMD_TUNED_VALUE, 176 177 CMD_MAX_NUM 178 }E_CMD_CODE; 179 180 typedef enum 181 { 182 pc_op_code = 0, 183 pc_if_freq, 184 pc_sound_sys, 185 pc_vif_vga_maximum_l, 186 pc_vif_vga_maximum_h, 187 pc_scan_mode, 188 pc_vif_top, 189 pc_gain_distribution_thr_l, 190 pc_gain_distribution_thr_h, 191 192 VIF_PARAM_MAX_NUM 193 }E_VIF_PARAM; 194 195 typedef enum 196 { 197 pc_system = 0, 198 199 SYS_PARAM_MAX_NUM 200 }E_SYS_PARAM; 201 202 typedef enum 203 { 204 SET_IF_FREQ = 0, 205 SET_SOUND_SYS, 206 VIF_INIT, 207 SET_VIF_HANDLER, 208 VIF_TOP_ADJUST, 209 210 VIF_CMD_MAX_NUM 211 }E_VIF_CMD; 212 213 typedef enum 214 { 215 TS_PARALLEL = 0, 216 TS_SERIAL = 1, 217 218 TS_MODE_MAX_NUM 219 }E_TS_MODE; 220 221 typedef enum 222 { 223 dac_op_code = 0, 224 dac_idac_ch0, 225 dac_idac_ch1, 226 227 DAC_PARAM_MAX_NUM 228 } 229 E_DAC_PARAM; 230 231 typedef enum 232 { 233 DAC_RUN_CALI = 0, 234 DAC_IDAC_ASSIGN, 235 236 DAC_CMD_MAX_NUM 237 } 238 E_DAC_CMD; 239 240 typedef enum 241 { 242 agc_ref_small, 243 agc_ref_large, 244 agc_ref_aci, 245 ripple_switch_th_l, 246 ripple_switch_th_h, 247 248 TUNED_PARAM_MAX_NUM 249 }E_TUNED_PARAM; 250 251 252 typedef struct 253 { 254 U8 cmd_code; 255 U8 param[64]; 256 } S_CMDPKTREG; 257 258 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3 259 #define REG_CMD_CTRL 0x20CC 260 #define REG_DTA_CTRL 0x20CD 261 #define REG_CMD_ADDR 0x20CE 262 #define REG_CMD_DATA 0x20CF 263 #endif 264 265 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4 266 #define REG_CMD_CTRL 0x2F1C 267 #define REG_DTA_CTRL 0x2F1D 268 #define REG_CMD_ADDR 0x2F1E 269 #define REG_CMD_DATA 0x2F1F 270 #endif 271 272 #define _REG_START REG_CMD_CTRL 273 #define _REG_END REG_CMD_CTRL 274 #define _REG_DRQ REG_DTA_CTRL 275 #define _REG_FSM REG_CMD_CTRL 276 #define _REG_ERR REG_DTA_CTRL 277 278 #define _BIT_START BIT1 279 #define _BIT_END BIT0 280 #define _BIT_DRQ BIT0 281 #define _BIT_FSM BIT3 282 #define _BIT_ERR BIT7 283 284 //-------------------------------------------------------------------- 285 typedef enum 286 { 287 // OP Mode Settings 288 p_opmode_rfagc_en = 0, 289 p_opmode_humdet_en, 290 p_opmode_dcr_en, 291 p_opmode_iqb_en, 292 p_opmode_auto_iq_swap, 293 p_opmode_auto_fsa_left, 294 p_opmode_auto_rfmax, 295 p_opmode_mode_forced, 296 p_opmode_cp_forced, 297 298 // Config Params 299 pc_config_rssi, 300 pc_config_zif, 301 pc_config_fc_l, 302 pc_config_fc_h, 303 pc_config_fs_l, 304 pc_config_fs_h, 305 pc_config_bw, 306 pc_config_fsa_left, 307 pc_config_rfmax, 308 pc_config_lp_sel, 309 pc_config_cp, 310 pc_config_mode, 311 pc_config_iq_swap, 312 pc_config_atv_system, 313 pc_config_serial_ts, 314 pc_config_ts_out_inv, 315 pc_config_data_swap, 316 pc_config_icfo_range, 317 318 DVBT_PARAM_LEN, 319 } DVBT_Param; 320 321 322 //-------------------------------------------------------------------- 323 EXTSEL BOOLEAN INTERN_DVBT_Reset ( void ); 324 EXTSEL BOOLEAN INTERN_DVBT_Active(BOOLEAN bEnable); 325 EXTSEL BOOLEAN INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, U8 param_cnt); 326 EXTSEL BOOLEAN INTERN_DVBT_Get_TPS_Parameter_Const( WORD * TSP_parameter); 327 EXTSEL BOOLEAN INTERN_DVBT_Exit ( void ); 328 //EXTSEL void MDrv_1210_IIC_Bypass_Mode(BOOLEAN enable); 329 //-------------------------------------------------------------------- 330 331 332 #undef EXTSEL 333 #endif 334 335