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Searched refs:REG_COMBO_GP_TOP_40_L (Results 1 – 25 of 44) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2080 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
2225 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
2287 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
2524 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
2533 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
4479 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
4492 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DhalHDCP.c293 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
302 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); /… in MHal_HDCP_HDCP14FillKey()
H A DregHDCP.h442 #define REG_COMBO_GP_TOP_40_L 0x40U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DhalHDCP.c293 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
302 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); /… in MHal_HDCP_HDCP14FillKey()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1377 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
1522 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
1584 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
1793 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
1802 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DhalHDCP.c355 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
364 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), 0); /… in MHal_HDCP_HDCP14FillKey()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DhalHDCP.c355 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
364 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), 0); /… in MHal_HDCP_HDCP14FillKey()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DhalHDCP.c355 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
364 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), 0); /… in MHal_HDCP_HDCP14FillKey()
H A DregHDCP.h442 #define REG_COMBO_GP_TOP_40_L 0x40U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DhalHDCP.c446 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
455 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); /… in MHal_HDCP_HDCP14FillKey()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DhalHDCP.c508 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
517 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), 0); /… in MHal_HDCP_HDCP14FillKey()
H A DregHDCP.h442 #define REG_COMBO_GP_TOP_40_L 0x40U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DhalHDCP.c514 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3… in MHal_HDCP_HDCP14FillKey()
523 …MHalHdcpRegMaskWrite(DEF_COMBO_GP_TOP_REG_BANK, REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), 0); /… in MHal_HDCP_HDCP14FillKey()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3291 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3454 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3542 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
3833 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
3842 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6139 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6152 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c3410 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3578 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3666 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
3943 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
3952 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6193 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6206 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3321 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3510 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3603 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
3933 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
3942 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6262 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6275 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c3410 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3578 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3666 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
3943 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
3952 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6193 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6206 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c3305 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3471 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3559 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
3878 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
3887 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6260 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6273 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3321 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3510 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3603 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
3933 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
3942 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6262 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6275 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3961 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
4124 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
4212 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
4505 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
4514 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6856 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6869 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3964 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
4127 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
4215 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
4508 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
4517 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6859 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6872 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c3494 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3660 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3748 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
4067 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
4076 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6630 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6643 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3964 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
4130 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
4218 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
4511 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
4520 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6862 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6875 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c3494 …W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0x05, 0x07); // [2]: Enable CPU write; [1]: disable SRAM read; [0… in Hal_HDCP22_PortInit()
3660 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(0), BMASK(2:0)); //enable XIU read in Hal_HDCP22_FetchMsg()
3748 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP22_SendMsg()
4067 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(3)|BIT(2)|BIT(0), BIT(3)|BIT(2)|BIT(0)); // [2]: CPU wri… in Hal_HDCP_initproductionkey()
4076 …HDCP_W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BIT(3)|BIT(2)|BIT(0)); // [2]: CPU write enable, [3]: 0: … in Hal_HDCP_initproductionkey()
6630 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, BIT(2)| BIT(0), BMASK(2:0)); //enable XIU write in Hal_HDCP_WriteKSVList()
6643 W2BYTEMSK(REG_COMBO_GP_TOP_40_L, 0, BMASK(2:0)); //disable XIU write in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DregHDCP.h442 #define REG_COMBO_GP_TOP_40_L 0x40U macro

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