| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/ |
| H A D | regHDCP.h | 402 #define REG_COMBO_GP_TOP_18_L 0x18U macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 716 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
764 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4242 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 727 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
775 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4351 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 798 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
846 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4357 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 727 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
775 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4351 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 788 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
836 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4301 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 798 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
846 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4357 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 719 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
767 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4925 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 719 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
767 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4928 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 854 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
902 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4485 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 719 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
767 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4931 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 854 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
902 …W2BYTEMSK(REG_COMBO_GP_TOP_18_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4485 W2BYTEMSK(REG_COMBO_GP_TOP_18_L, BIT(12), BIT(12)); // [12]: enable DVI function (P1) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 6532 #define REG_COMBO_GP_TOP_18_L (REG_COMBO_GP_TOP_BASE + 0x30) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 6534 #define REG_COMBO_GP_TOP_18_L (REG_COMBO_GP_TOP_BASE + 0x30) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 6524 #define REG_COMBO_GP_TOP_18_L (REG_COMBO_GP_TOP_BASE + 0x30) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 6534 #define REG_COMBO_GP_TOP_18_L (REG_COMBO_GP_TOP_BASE + 0x30) macro
|