| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 379 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, (BIT(4)| BIT(2)| BIT(0)), BMASK(4:0)); // [3]: reg_pix_sd_clk_div… in _Hal_tmds_HDMI20PHYSetting()
2028 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
3371 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(3), BIT(3)); // [3]: reg_pix_sd_clk_div2_en; in Hal_HDMI_AVG_ScaleringDown()
3377 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, 0, BIT(3)); // [3]: reg_pix_sd_clk_div2_en; in Hal_HDMI_AVG_ScaleringDown()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 476 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(3)| BIT(2)| BIT(0)), BMASK(3:0)); // [3]: re… in _Hal_tmds_HDMI20PHYSetting()
481 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bAvaageModeFlag? BIT(3): 0, BIT(3)); in _Hal_tmds_HDMI20PHYSetting()
511 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bSettingFlag? 0: BIT(3), BIT(3)); // [4]: reg_pix_420t_clk_div2_e… in _Hal_tmds_YUV420PHYSetting()
2764 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/ |
| H A D | regHDCP.h | 394 #define REG_COMBO_GP_TOP_10_L 0x10U macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 708 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
758 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4241 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 719 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
769 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4350 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 790 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
840 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4356 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 719 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
769 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4350 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 780 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
830 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4300 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 790 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
840 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4356 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 711 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
761 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4924 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 711 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
761 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4927 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 846 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
896 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4484 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 711 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
761 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4930 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 846 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bHDMI20Flag? 0: (BIT(2)| BIT(0)), BMASK(3:0)); // [3]: reg_pix_sd… in _Hal_tmds_HDMI20PHYSetting()
896 …W2BYTEMSK(REG_COMBO_GP_TOP_10_L, bYUV420Flag? BIT(2): 0, BMASK(4:0)); // [4]: reg_pix_420t_clk_div… in _Hal_tmds_YUV420PHYSetting()
4484 W2BYTEMSK(REG_COMBO_GP_TOP_10_L, BIT(12), BIT(12)); // [12]: enable DVI function (P0) in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 6516 #define REG_COMBO_GP_TOP_10_L (REG_COMBO_GP_TOP_BASE + 0x20) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 6518 #define REG_COMBO_GP_TOP_10_L (REG_COMBO_GP_TOP_BASE + 0x20) macro
|