Searched refs:REG_CLKGEN1_DC0_SYTNTH (Results 1 – 2 of 2) sorted by relevance
2288 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~REG_CLKGEN1_STC4_CW_SEL; in HAL_TSP_STC_Init()2289 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~REG_CLKGEN1_STC5_CW_SEL; in HAL_TSP_STC_Init()2325 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC4_CW_EN); in HAL_TSP_STC_Init()2326 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) |= REG_CLKGEN1_STC4_CW_EN; in HAL_TSP_STC_Init()2327 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC4_CW_EN); in HAL_TSP_STC_Init()2328 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC5_CW_EN); in HAL_TSP_STC_Init()2329 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) |= REG_CLKGEN1_STC5_CW_EN; in HAL_TSP_STC_Init()2330 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC5_CW_EN); in HAL_TSP_STC_Init()2462 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~REG_CLKGEN1_STC4_CW_SEL; in HAL_TSP_SetSTCSynth()2469 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC4_CW_EN); in HAL_TSP_SetSTCSynth()[all …]
177 #define REG_CLKGEN1_DC0_SYTNTH 0x5A macro