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Searched refs:REG_CLKGEN0_TSN_CLK_MASK (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c209 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1924 …GEN2_TSN_TS4TS5) = (TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_TS4TS5) & ~(REG_CLKGEN0_TSN_CLK_MASK << u16S2p… in HAL_TSP_TsOutPadCfg()
2194 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2199 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2204 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2209 …u32data = TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN2_TSN_CL… in HAL_TSP_SelPad_ClkInv()
3211 …P_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) >> REG_CLKGEN2_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3230 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3237 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3244 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c223 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1946 …GEN2_TSN_TS4TS5) = (TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_TS4TS5) & ~(REG_CLKGEN0_TSN_CLK_MASK << u16S2p… in HAL_TSP_TsOutPadCfg()
2216 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2221 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2226 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2231 …u32data = TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN2_TSN_CL… in HAL_TSP_SelPad_ClkInv()
3237 …P_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) >> REG_CLKGEN2_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3256 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3263 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3270 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c228 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1869 …EG_CLKGEN0_TSN_TS4) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_TS4) & ~(REG_CLKGEN0_TSN_CLK_MASK << REG_CL… in HAL_TSP_TsOutPadCfg()
2074 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2079 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2084 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2089 …u32data = TSP_CLKGEN1_REG(REG_CLKGEN1_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN1_TSN_CL… in HAL_TSP_SelPad_ClkInv()
3175 …P_CLKGEN1_REG(REG_CLKGEN1_TSN_CLKFI) >> REG_CLKGEN1_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3194 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3201 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3208 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c211 #define REG_CLKGEN0_TSN_CLK_MASK 0x1F macro
1865 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLKTS4) & ~(REG_CLKGEN0_TSN_CLK_MASK<<REG_CLKGEN0_TSN_CLK_TS4_SHI… in HAL_TSP_TsOutPadCfg()
2040 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2045 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2050 …u32data = TSP_CLKGEN1_REG(REG_CLKGEN1_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN1_TSN_CL… in HAL_TSP_SelPad_ClkInv()
2939 …P_CLKGEN1_REG(REG_CLKGEN1_TSN_CLKFI) >> REG_CLKGEN1_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
2957 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
2964 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c228 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1972 …EG_CLKGEN2_TSN_TS4) = (TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_TS4) & ~(REG_CLKGEN0_TSN_CLK_MASK << u16S2p… in HAL_TSP_TsOutPadCfg()
2269 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2274 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2279 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2284 …u32data = TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN2_TSN_CL… in HAL_TSP_SelPad_ClkInv()
3423 …P_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) >> REG_CLKGEN2_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3442 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3449 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3456 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c228 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1972 …EG_CLKGEN2_TSN_TS4) = (TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_TS4) & ~(REG_CLKGEN0_TSN_CLK_MASK << u16S2p… in HAL_TSP_TsOutPadCfg()
2269 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2274 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2279 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2284 …u32data = TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN2_TSN_CL… in HAL_TSP_SelPad_ClkInv()
3406 …P_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) >> REG_CLKGEN2_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3425 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3432 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3439 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c228 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
2033 …GEN2_TSN_TS4TS5) = (TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_TS4TS5) & ~(REG_CLKGEN0_TSN_CLK_MASK << u16S2p… in HAL_TSP_TsOutPadCfg()
2340 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2345 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2350 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2355 …u32data = TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN2_TSN_CL… in HAL_TSP_SelPad_ClkInv()
3502 …P_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) >> REG_CLKGEN2_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3521 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3528 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3535 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c228 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1994 …GEN2_TSN_TS4TS5) = (TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_TS4TS5) & ~(REG_CLKGEN0_TSN_CLK_MASK << u16S2p… in HAL_TSP_TsOutPadCfg()
2301 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2306 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2311 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2316 …u32data = TSP_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN2_TSN_CL… in HAL_TSP_SelPad_ClkInv()
3463 …P_CLKGEN2_REG(REG_CLKGEN2_TSN_CLKFI) >> REG_CLKGEN2_TSN_CLK_TSFI_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3482 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3489 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
3496 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c189 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1371 …EG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< u32Shft… in HAL_TSP_SelPad_ClkInv()
1655 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
1662 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c190 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1374 …EG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< u32Shft… in HAL_TSP_SelPad_ClkInv()
1645 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
1652 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c190 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL macro
1372 …EG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< u32Shft… in HAL_TSP_SelPad_ClkInv()
1656 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()
1663 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK; in HAL_TSP_GetTSIF_Status()