Searched refs:REG_CLKGEN0_TS5_CLK (Results 1 – 2 of 2) sorted by relevance
530 …TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) & ~(REG_CLKGEN0_TS_MA… in HAL_TSP_Power()624 …TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK),(REG_CLKGEN0_T… in HAL_TSP_Power()899 …TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) & ~(REG_CLKGEN0_TS_MA… in HAL_TSP_TSIF_SelPad()946 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS5_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()975 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS5_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkInv()1028 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS5_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()1074 …u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS5_SHIFT)) … in HAL_TSP_TSIF_SelPad_ClkDis()1111 … TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS5_SHIFT)); in HAL_TSP_TSIF_SelPad_ClkDis()
101 #define REG_CLKGEN0_TS5_CLK 0x6B macro