| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 803 #define REG_CKG_S2_FICLK2_F2 (REG_CLKGEN2_BASE + 0xC3 ) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 785 #define REG_CKG_S2_FICLK2_F2 (REG_CLKGEN2_BASE + 0xC3 ) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 849 #define REG_CKG_S2_FICLK2_F2 (REG_CLKGEN2_BASE + 0xC3 ) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 963 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 918 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 975 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 912 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 980 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 967 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_sc.c | 323 …MDrv_WriteByteMask(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_e… in Hal_SC_set_ficlk()
327 …MDrv_WriteByteMask(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mvideo.c | 554 …MDrv_WriteRegBit(REG_CKG_S2_FICLK2_F2, ENABLE, CKG_FICLK2_F2_GATED); // Enable … in MApi_XC_Exit_U2()
1238 …MDrv_WriteByteMask(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); /… in _MApi_XC_Init_WithoutCreateMutex()
1239 …MDrv_WriteRegBit(REG_CKG_S2_FICLK2_F2, DISABLE, CKG_S2_FICLK2_F2_INVERT); // Not… in _MApi_XC_Init_WithoutCreateMutex()
1240 …MDrv_WriteRegBit(REG_CKG_S2_FICLK2_F2, DISABLE, CKG_S2_FICLK2_F2_GATED); // Ena… in _MApi_XC_Init_WithoutCreateMutex()
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| H A D | mvideo.c.0 | 551 …MDrv_WriteRegBit(REG_CKG_S2_FICLK2_F2, ENABLE, CKG_FICLK2_F2_GATED); // Enable …
1235 …MDrv_WriteByteMask(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); /…
1236 …MDrv_WriteRegBit(REG_CKG_S2_FICLK2_F2, DISABLE, CKG_S2_FICLK2_F2_INVERT); // Not…
1237 …MDrv_WriteRegBit(REG_CKG_S2_FICLK2_F2, DISABLE, CKG_S2_FICLK2_F2_GATED); // Ena…
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_sc.c | 402 …MDrv_WriteByteMask(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_e… in Hal_SC_set_ficlk()
406 …MDrv_WriteByteMask(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_sc.c | 412 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk in Hal_SC_set_ficlk()
416 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_sc.c | 387 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk in Hal_SC_set_ficlk()
391 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_sc.c | 397 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk in Hal_SC_set_ficlk()
401 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_sc.c | 410 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk in Hal_SC_set_ficlk()
414 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_sc.c | 410 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk in Hal_SC_set_ficlk()
414 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_sc.c | 410 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk in Hal_SC_set_ficlk()
414 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_sc.c | 410 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk in Hal_SC_set_ficlk()
414 … W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk in Hal_SC_set_ficlk()
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