| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mdrv_sc_pip.c | 723 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_INVERT); // Not Invert in MDrv_XC_EnableCLK_for_SUB()
724 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock in MDrv_XC_EnableCLK_for_SUB()
739 MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_INVERT); // Not Invert in MDrv_XC_EnableCLK_for_SUB()
740 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MDrv_XC_EnableCLK_for_SUB()
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| H A D | mdrv_sc_pip.c.0 | 723 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_INVERT); // Not Invert
724 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock
739 MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_INVERT); // Not Invert
740 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
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| H A D | mvideo.c | 484 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MApi_XC_Exit_U2()
527 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MApi_XC_Exit_U2()
567 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MApi_XC_Exit_U2()
1118 …MDrv_WriteByteMask(REG_CKG_FICLK_F1, CKG_FICLK_F1_FLK, CKG_FICLK_F1_MASK); // select FClk fir… in _MApi_XC_Init_WithoutCreateMutex()
1119 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_INVERT); // Not Invert in _MApi_XC_Init_WithoutCreateMutex()
1120 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock in _MApi_XC_Init_WithoutCreateMutex()
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| H A D | mvideo.c.0 | 481 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
524 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
564 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
1115 …MDrv_WriteByteMask(REG_CKG_FICLK_F1, CKG_FICLK_F1_FLK, CKG_FICLK_F1_MASK); // select FClk fir…
1116 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_INVERT); // Not Invert
1117 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | mhal_xc_chip_config.h | 486 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | mhal_xc_chip_config.h | 486 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 641 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 639 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 654 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 660 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 660 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 662 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| H A D | mhal_xc_chip_config.h.0 | 661 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 636 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 736 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 696 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 748 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 686 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 753 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 740 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_sc.c | 653 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_IDCLK1, CKG_FICLK_F1_MASK); // clk_idclk1 in Hal_SC_set_ficlk()
657 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_FCLK, CKG_FICLK_F1_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_sc.c | 587 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_IDCLK1, CKG_FICLK_F1_MASK); // clk_idclk1 in Hal_SC_set_ficlk()
591 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_FCLK, CKG_FICLK_F1_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_sc.c | 653 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_IDCLK1, CKG_FICLK_F1_MASK); // clk_idclk1 in Hal_SC_set_ficlk()
657 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_FCLK, CKG_FICLK_F1_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_sc.c | 784 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_IDCLK1, CKG_FICLK_F1_MASK); // clk_idclk1 in Hal_SC_set_ficlk()
788 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_FCLK, CKG_FICLK_F1_MASK); // clk_fclk in Hal_SC_set_ficlk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_sc.c | 399 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_IDCLK1, CKG_FICLK_F1_MASK); // clk_idclk1 in Hal_SC_set_ficlk()
403 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_FCLK, CKG_FICLK_F1_MASK); // clk_fclk in Hal_SC_set_ficlk()
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