| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 628 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 626 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 608 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 708 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 668 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 720 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 658 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 725 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 712 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_sc.c | 5054 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
5056 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_sc.c | 5190 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
5192 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_sc.c | 6296 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
6298 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_sc.c | 7019 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
7021 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_sc.c | 7057 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
7059 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_sc.c | 7587 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
7589 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_sc.c | 7610 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
7612 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_sc.c | 7822 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
7824 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_sc.c | 7823 … MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED); in Hal_SC_set_edclk()
7825 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK); in Hal_SC_set_edclk()
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