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Searched refs:REG_BDMA_BASE (Results 1 – 5 of 5) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/ca2/
H A DregCA.h182 #define REG_BDMA_BASE (0x00900UL * 2) macro
183 #define REG_BDMA_CTRL (REG_BDMA_BASE + 0x0)
184 #define REG_BDMA_STATUS (REG_BDMA_BASE + 0x1*4)
185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4)
186 #define REG_BDMA_SRC_ADDR_L (REG_BDMA_BASE + 0x4*4)
187 #define REG_BDMA_SRC_ADDR_H (REG_BDMA_BASE + 0x5*4)
188 #define REG_BDMA_DST_ADDR_L (REG_BDMA_BASE + 0x6*4)
189 #define REG_BDMA_DST_ADDR_H (REG_BDMA_BASE + 0x7*4)
190 #define REG_BDMA_SIZE_L (REG_BDMA_BASE + 0x8*4)
191 #define REG_BDMA_SIZE_H (REG_BDMA_BASE + 0x9*4)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/ca2/
H A DregCA.h182 #define REG_BDMA_BASE (0x00900UL * 2) macro
183 #define REG_BDMA_CTRL (REG_BDMA_BASE + 0x0)
184 #define REG_BDMA_STATUS (REG_BDMA_BASE + 0x1*4)
185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4)
186 #define REG_BDMA_SRC_ADDR_L (REG_BDMA_BASE + 0x4*4)
187 #define REG_BDMA_SRC_ADDR_H (REG_BDMA_BASE + 0x5*4)
188 #define REG_BDMA_DST_ADDR_L (REG_BDMA_BASE + 0x6*4)
189 #define REG_BDMA_DST_ADDR_H (REG_BDMA_BASE + 0x7*4)
190 #define REG_BDMA_SIZE_L (REG_BDMA_BASE + 0x8*4)
191 #define REG_BDMA_SIZE_H (REG_BDMA_BASE + 0x9*4)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/ca2/
H A DregCA.h182 #define REG_BDMA_BASE (0x00900UL * 2) macro
183 #define REG_BDMA_CTRL (REG_BDMA_BASE + 0x0)
184 #define REG_BDMA_STATUS (REG_BDMA_BASE + 0x1*4)
185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4)
186 #define REG_BDMA_SRC_ADDR_L (REG_BDMA_BASE + 0x4*4)
187 #define REG_BDMA_SRC_ADDR_H (REG_BDMA_BASE + 0x5*4)
188 #define REG_BDMA_DST_ADDR_L (REG_BDMA_BASE + 0x6*4)
189 #define REG_BDMA_DST_ADDR_H (REG_BDMA_BASE + 0x7*4)
190 #define REG_BDMA_SIZE_L (REG_BDMA_BASE + 0x8*4)
191 #define REG_BDMA_SIZE_H (REG_BDMA_BASE + 0x9*4)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/ca2/
H A DregCA.h182 #define REG_BDMA_BASE (0x00900UL * 2) macro
183 #define REG_BDMA_CTRL (REG_BDMA_BASE + 0x0)
184 #define REG_BDMA_STATUS (REG_BDMA_BASE + 0x1*4)
185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4)
186 #define REG_BDMA_SRC_ADDR_L (REG_BDMA_BASE + 0x4*4)
187 #define REG_BDMA_SRC_ADDR_H (REG_BDMA_BASE + 0x5*4)
188 #define REG_BDMA_DST_ADDR_L (REG_BDMA_BASE + 0x6*4)
189 #define REG_BDMA_DST_ADDR_H (REG_BDMA_BASE + 0x7*4)
190 #define REG_BDMA_SIZE_L (REG_BDMA_BASE + 0x8*4)
191 #define REG_BDMA_SIZE_H (REG_BDMA_BASE + 0x9*4)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/ca2/
H A DregCA.h182 #define REG_BDMA_BASE (0x00900UL * 2) macro
183 #define REG_BDMA_CTRL (REG_BDMA_BASE + 0x0)
184 #define REG_BDMA_STATUS (REG_BDMA_BASE + 0x1*4)
185 #define REG_BDMA_SRC_SEL (REG_BDMA_BASE + 0x2*4)
186 #define REG_BDMA_SRC_ADDR_L (REG_BDMA_BASE + 0x4*4)
187 #define REG_BDMA_SRC_ADDR_H (REG_BDMA_BASE + 0x5*4)
188 #define REG_BDMA_DST_ADDR_L (REG_BDMA_BASE + 0x6*4)
189 #define REG_BDMA_DST_ADDR_H (REG_BDMA_BASE + 0x7*4)
190 #define REG_BDMA_SIZE_L (REG_BDMA_BASE + 0x8*4)
191 #define REG_BDMA_SIZE_H (REG_BDMA_BASE + 0x9*4)