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Searched refs:REG_ADC_ATOP_50_L (Results 1 – 25 of 37) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_adc.c2129 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2134 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2199 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_adc.c2129 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2134 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2199 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_adc.c2091 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2096 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2161 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_adc.c2091 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2096 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2161 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_adc.c2107 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2112 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2177 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_adc.c2091 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2096 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2161 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_adc.c2221 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2226 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2291 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_adc.c2213 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2218 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2283 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_adc.c2213 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2218 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2283 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_adc.c2213 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2218 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2283 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_adc.c2213 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, BIT(0) , BIT(0) ); in Hal_ADC_set_cvbs_out()
2218 MDrv_WriteByteMask(REG_ADC_ATOP_50_L, 0x00 , BIT(0) ); in Hal_ADC_set_cvbs_out()
2283 if ( MDrv_ReadByte(REG_ADC_ATOP_50_L ) & BIT(0) ) in Hal_ADC_is_cvbs_out_enabled()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
H A Dmhal_adctbl.c2474 { DRV_ADC_REG(REG_ADC_ATOP_50_L), 0xEF, 0x01, 0x00/*$OFF*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
H A Dmhal_adctbl.c2474 { DRV_ADC_REG(REG_ADC_ATOP_50_L), 0xEF, 0x01, 0x00/*$OFF*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
H A Dmhal_adctbl.c2425 { DRV_ADC_REG(REG_ADC_ATOP_50_L), 0xEF, 0x01, 0x00/*$OFF*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_adc_atop.h265 #define REG_ADC_ATOP_50_L (REG_ADC_ATOP_BASE + 0xA0) macro
H A Dmhal_adctbl.c2474 { DRV_ADC_REG(REG_ADC_ATOP_50_L), 0xEF, 0x01, 0x00/*$OFF*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c2528 { DRV_ADC_REG(REG_ADC_ATOP_50_L), 0xEF, 0x01, 0x00/*$OFF*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c2528 { DRV_ADC_REG(REG_ADC_ATOP_50_L), 0xEF, 0x01, 0x00/*$OFF*/,

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