| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | halTSP.c | 138 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value)) macro
346 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
456 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_Reset()
457 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
466 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
472 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
474 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
475 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
476 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
477 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | halTSP.c | 120 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value)) macro
269 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
370 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_Reset()
371 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
380 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
386 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
388 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
389 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
390 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
391 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | halTSP.c | 141 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value)) macro
348 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
446 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_Reset()
447 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
456 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
462 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
464 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
465 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
466 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
467 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | halTSP.c | 113 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value)) macro
261 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
345 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_Reset()
346 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
355 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
361 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
363 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
364 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
365 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
366 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/ |
| H A D | halTSP.c | 121 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value)) macro
284 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
297 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_DIS_NULL_PKT); in HAL_TSP_HwPatch()
420 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
425 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
552 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE); in HAL_TSP_Power()
643 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
676 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
686 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
772 REG16_CLR(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_TS_IF_EN); in HAL_TSP_TSIF_LiveEn()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/multi_pvr/ |
| H A D | halMultiPVR.c | 150 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value)) macro
274 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_DIS_NULL_PKT); in HAL_MultiPVR_Init()
285 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_EN); in HAL_MultiPVR_Exit()
288 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_71, CFG_MULTI_PVR_71_REG_INPUT_SRC_MASK); in HAL_MultiPVR_Exit()
291 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_RECORD_TS); in HAL_MultiPVR_Exit()
302 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_DMA_FLUSH_EN); in HAL_MultiPVR_FlushData()
315 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_MASK_SCR_PVR_EN); in HAL_MultiPVR_Skip_Scrmb()
329 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_PVR_BLOCK_DISABLE); in HAL_MultiPVR_Block_Dis()
418 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_PAUSE); in HAL_MultiPVR_Pause()
428 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_RECORD_ALL); in HAL_MultiPVR_RecPid()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/dscmb/ |
| H A D | halDSCMB.c | 134 #define REG16_CLR(reg, value); REG16_W(reg, _CLR_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/dscmb/ |
| H A D | halDSCMB.c | 134 #define REG16_CLR(reg, value); REG16_W(reg, _CLR_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/dscmb/ |
| H A D | halDSCMB.c | 134 #define REG16_CLR(reg, value); REG16_W(reg, _CLR_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/dscmb/ |
| H A D | halDSCMB.c | 134 #define REG16_CLR(reg, value); REG16_W(reg, _CLR_(REG16_R(reg), value)); macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/dscmb/ |
| H A D | halDSCMB.c | 134 #define REG16_CLR(reg, value); REG16_W(reg, _CLR_(REG16_R(reg), value)); macro
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