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Searched refs:R2_REG_RST_BASE (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/cpu/hal/mooney/cpu/
H A DregCPU.h136 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4UL) macro
H A DhalCPU.c551 … HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); //reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/maldives/cpu/
H A DregCPU.h135 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4) macro
H A DhalCPU.c478 HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); // reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/mainz/cpu/
H A DregCPU.h136 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4UL) macro
H A DhalCPU.c549 … HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); //reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/messi/cpu/
H A DregCPU.h136 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4UL) macro
H A DhalCPU.c549 … HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); //reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/mustang/cpu/
H A DregCPU.h135 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4) macro
H A DhalCPU.c478 HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); // reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/k6lite/cpu/
H A DregCPU.h135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
H A DhalCPU.c485 HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); // reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/k7u/cpu/
H A DregCPU.h135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
H A DhalCPU.c485 HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); // reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/curry/cpu/
H A DregCPU.h135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/k6/cpu/
H A DregCPU.h135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
H A DhalCPU.c485 HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); // reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/kano/cpu/
H A DregCPU.h135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
H A DhalCPU.c485 HAL_COPRO_RegWrite2Byte(R2_REG_RST_BASE, base_addr); // reset vector address 0x0(64K alignment) in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/manhattan/cpu/
H A DregCPU.h162 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/macan/cpu/
H A DregCPU.h162 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/maxim/cpu/
H A DregCPU.h172 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/maserati/cpu/
H A DregCPU.h174 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/M7621/cpu/
H A DregCPU.h172 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/M7821/cpu/
H A DregCPU.h173 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL) macro

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