xref: /utopia/UTPA2-700.0.x/modules/cpu/hal/k6/cpu/regCPU.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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/// @file  regMVD.h
/// @brief Hardware register definition for Video Decoder
/// @author MStar Semiconductor Inc.
//
///////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_COPRO_H_
#define _REG_COPRO_H_


////////////////////////////////////////////////////////////////////////////////
// Constant & Macro Definition
////////////////////////////////////////////////////////////////////////////////
//------------------------------------------------------------------------------
// Base Address
//------------------------------------------------------------------------------
// For Co-Processor
#define R2_REG_BASE                             0x003500UL    //0x122A00 //sec_r2
#define R2_MAULV1_REG_BASE                      0x003600UL    //0x122B00 //sec_r2_maulv1

// For Non-PM
#define NPM_REG_CLKGEN0                         0x000B00UL    //0x100b00 //clkgen0
#define NPM_REG_CLKGEN1                         0x003300UL    //0x103300 //clkgen1
#define NPM_REG_CHIPTOP                         0x001E00UL    //0x101E00 //chiptop
#define NPM_REG_MIU0                            0x001200UL    //0x101200 //miu0
#define NPM_REG_MIU1                            0x000600UL    //0x100600 //miu1
#define NPM_REG_ANAMISC                         0x010C00UL    //0x110c00 //ana misc
//For PM
#define PM_REG_BASE_SLEEP                       0x000E00UL    //0x002E00 //pm_sleep
#define PM_REG_BASE_MISC                        0x002E00UL    //0x002E00 //pm_misc

//------------------------------------------------------------------------------
// MCU and PIU Reg
//------------------------------------------------------------------------------
// For Co-Processor
#define R2_REG_STOP                             (R2_REG_BASE+0x0080UL)
#define R2_REG_SDR_LO_INST_BASE                 (R2_REG_BASE+0x0082UL)
#define R2_REG_SDR_HI_INST_BASE                 (R2_REG_BASE+0x0084UL)
#define R2_REG_SDR_LO_DATA_BASE                 (R2_REG_BASE+0x0086UL)
#define R2_REG_SDR_HI_DATA_BASE                 (R2_REG_BASE+0x0088UL)
#define R2_REG_RIU_BASE                         (R2_REG_BASE+0x008AUL)
#define R2_REG_RST_BASE                         (R2_REG_BASE+0x00B4UL)
#define R2_REG_IO1_BASE                         (R2_REG_BASE+0x00AAUL)
#define R2_REG_SPI_BASE                         (R2_REG_BASE+0x0090UL)
#define R2_REG_SPI_BASE1                        (R2_REG_BASE+0x00ACUL)
#define R2_REG_DQMEM_BASE                       (R2_REG_BASE+0x009CUL)
#define R2_REG_SPACE_EN                         (R2_REG_BASE+0x00B0UL)
#define R2_REG_QMEM_MASK_HIGH                   (R2_REG_BASE+0x00A0UL)
#define R2_REG_QMEM_BASE_HIGH                   (R2_REG_BASE+0x009CUL)

#define R2_MAULV1_REG                           (R2_MAULV1_REG_BASE + 0x0002UL)    //0x122B00 //sec_r2_maulv1
#define NPM_REG_CPU_CLOCK                       (NPM_REG_PORT_STATUS + 0x001E)

#define REG_CPU_DETECT                          (0x1ee2)

// For Non-PM
#define NPM_REG_CLKGEN1_SECR2                   (NPM_REG_CLKGEN1+0x007AUL) //3D*2
#define NPM_REG_CHIPTOP_UART                    (NPM_REG_CHIPTOP+0x00A6UL)
#define NPM_REG_MIPS_PLLCLK                     (NPM_REG_ANAMISC+0x0026UL)
#define NPM_REG_LPF_LOW                         (NPM_REG_ANAMISC + 0x00C0UL)
#define NPM_REG_LPF_HIGH                        (NPM_REG_ANAMISC + 0x00C2UL)

// For PM
#define PM_REG_CPUX_SW_RSTZ                     (PM_REG_BASE_SLEEP+0x0052UL)
#define NPM_REG_CLKGEN0_SECR2                   (NPM_REG_CLKGEN0+0x0062)

#define NONE_CACHEABLE                          0x80000000UL

#endif // _REG_COPRO_H_