xref: /utopia/UTPA2-700.0.x/modules/cpu/hal/k6lite/cpu/regCPU.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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94 /// @file  regMVD.h
95 /// @brief Hardware register definition for Video Decoder
96 /// @author MStar Semiconductor Inc.
97 //
98 ///////////////////////////////////////////////////////////////////////////////////
99 
100 #ifndef _REG_COPRO_H_
101 #define _REG_COPRO_H_
102 
103 
104 ////////////////////////////////////////////////////////////////////////////////
105 // Constant & Macro Definition
106 ////////////////////////////////////////////////////////////////////////////////
107 //------------------------------------------------------------------------------
108 // Base Address
109 //------------------------------------------------------------------------------
110 // For Co-Processor
111 #define R2_REG_BASE                             0x003500UL    //0x122A00 //sec_r2
112 #define R2_MAULV1_REG_BASE                      0x003600UL    //0x122B00 //sec_r2_maulv1
113 
114 // For Non-PM
115 #define NPM_REG_CLKGEN0                         0x000B00UL    //0x100b00 //clkgen0
116 #define NPM_REG_CLKGEN1                         0x003300UL    //0x103300 //clkgen1
117 #define NPM_REG_CHIPTOP                         0x001E00UL    //0x101E00 //chiptop
118 #define NPM_REG_MIU0                            0x001200UL    //0x101200 //miu0
119 #define NPM_REG_MIU1                            0x000600UL    //0x100600 //miu1
120 #define NPM_REG_ANAMISC                         0x010C00UL    //0x110c00 //ana misc
121 //For PM
122 #define PM_REG_BASE_SLEEP                       0x000E00UL    //0x002E00 //pm_sleep
123 #define PM_REG_BASE_MISC                        0x002E00UL    //0x002E00 //pm_misc
124 
125 //------------------------------------------------------------------------------
126 // MCU and PIU Reg
127 //------------------------------------------------------------------------------
128 // For Co-Processor
129 #define R2_REG_STOP                             (R2_REG_BASE+0x0080UL)
130 #define R2_REG_SDR_LO_INST_BASE                 (R2_REG_BASE+0x0082UL)
131 #define R2_REG_SDR_HI_INST_BASE                 (R2_REG_BASE+0x0084UL)
132 #define R2_REG_SDR_LO_DATA_BASE                 (R2_REG_BASE+0x0086UL)
133 #define R2_REG_SDR_HI_DATA_BASE                 (R2_REG_BASE+0x0088UL)
134 #define R2_REG_RIU_BASE                         (R2_REG_BASE+0x008AUL)
135 #define R2_REG_RST_BASE                         (R2_REG_BASE+0x00B4UL)
136 #define R2_REG_IO1_BASE                         (R2_REG_BASE+0x00AAUL)
137 #define R2_REG_SPI_BASE                         (R2_REG_BASE+0x0090UL)
138 #define R2_REG_SPI_BASE1                        (R2_REG_BASE+0x00ACUL)
139 #define R2_REG_DQMEM_BASE                       (R2_REG_BASE+0x009CUL)
140 #define R2_REG_SPACE_EN                         (R2_REG_BASE+0x00B0UL)
141 #define R2_REG_QMEM_MASK_HIGH                   (R2_REG_BASE+0x00A0UL)
142 #define R2_REG_QMEM_BASE_HIGH                   (R2_REG_BASE+0x009CUL)
143 
144 #define R2_MAULV1_REG                           (R2_MAULV1_REG_BASE + 0x0002UL)    //0x122B00 //sec_r2_maulv1
145 #define NPM_REG_CPU_CLOCK                       (NPM_REG_PORT_STATUS + 0x001E)
146 
147 #define REG_CPU_DETECT                          (0x1ee2)
148 
149 // For Non-PM
150 #define NPM_REG_CLKGEN1_SECR2                   (NPM_REG_CLKGEN1+0x007AUL) //3D*2
151 #define NPM_REG_CHIPTOP_UART                    (NPM_REG_CHIPTOP+0x00A6UL)
152 #define NPM_REG_MIPS_PLLCLK                     (NPM_REG_ANAMISC+0x0026UL)
153 #define NPM_REG_LPF_LOW                         (NPM_REG_ANAMISC + 0x00C0UL)
154 #define NPM_REG_LPF_HIGH                        (NPM_REG_ANAMISC + 0x00C2UL)
155 
156 // For PM
157 #define PM_REG_CPUX_SW_RSTZ                     (PM_REG_BASE_SLEEP+0x0052UL)
158 #define NPM_REG_CLKGEN0_SECR2                   (NPM_REG_CLKGEN0+0x0062)
159 
160 #define NONE_CACHEABLE                          0x80000000UL
161 
162 #endif // _REG_COPRO_H_
163