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Searched refs:R2_REG_BASE (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/cpu/hal/mooney/cpu/
H A DregCPU.h110 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
131 #define R2_REG_STOP (R2_REG_BASE + 0x0080UL)
132 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE + 0x0082UL)
133 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE + 0x0084UL)
134 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE + 0x0086UL)
135 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE + 0x0088UL)
136 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4UL)
137 #define R2_REG_IO1_BASE (R2_REG_BASE + 0x00AAUL)
138 #define R2_REG_SPACE_EN (R2_REG_BASE + 0x00B0UL)
139 #define R2_REG_QMEM_MASK_HIGH (R2_REG_BASE + 0x00A0UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/maldives/cpu/
H A DregCPU.h111 #define R2_REG_BASE 0x022A00 //0x122A00 //sec_r2 macro
130 #define R2_REG_STOP (R2_REG_BASE + 0x0080)
131 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE + 0x0082)
132 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE + 0x0084)
133 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE + 0x0086)
134 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE + 0x0088)
135 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4)
136 #define R2_REG_RIU_BASE (R2_REG_BASE + 0x008A)
137 #define R2_REG_IO1_BASE (R2_REG_BASE + 0x00AA)
138 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/mainz/cpu/
H A DregCPU.h110 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
131 #define R2_REG_STOP (R2_REG_BASE + 0x0080UL)
132 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE + 0x0082UL)
133 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE + 0x0084UL)
134 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE + 0x0086UL)
135 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE + 0x0088UL)
136 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4UL)
137 #define R2_REG_IO1_BASE (R2_REG_BASE + 0x00AAUL)
138 #define R2_REG_SPACE_EN (R2_REG_BASE + 0x00B0UL)
139 #define R2_REG_QMEM_MASK_HIGH (R2_REG_BASE + 0x00A0UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/messi/cpu/
H A DregCPU.h110 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
131 #define R2_REG_STOP (R2_REG_BASE + 0x0080UL)
132 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE + 0x0082UL)
133 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE + 0x0084UL)
134 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE + 0x0086UL)
135 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE + 0x0088UL)
136 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4UL)
137 #define R2_REG_IO1_BASE (R2_REG_BASE + 0x00AAUL)
138 #define R2_REG_SPACE_EN (R2_REG_BASE + 0x00B0UL)
139 #define R2_REG_QMEM_MASK_HIGH (R2_REG_BASE + 0x00A0UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/mustang/cpu/
H A DregCPU.h111 #define R2_REG_BASE 0x022A00 //0x122A00 //sec_r2 macro
130 #define R2_REG_STOP (R2_REG_BASE + 0x0080)
131 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE + 0x0082)
132 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE + 0x0084)
133 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE + 0x0086)
134 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE + 0x0088)
135 #define R2_REG_RST_BASE (R2_REG_BASE + 0x00B4)
136 #define R2_REG_RIU_BASE (R2_REG_BASE + 0x008A)
137 #define R2_REG_IO1_BASE (R2_REG_BASE + 0x00AA)
138 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/k6lite/cpu/
H A DregCPU.h111 #define R2_REG_BASE 0x003500UL //0x122A00 //sec_r2 macro
129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
130 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
131 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
132 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
133 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
134 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
136 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
137 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/k7u/cpu/
H A DregCPU.h111 #define R2_REG_BASE 0x003500UL //0x122A00 //sec_r2 macro
129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
130 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
131 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
132 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
133 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
134 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
136 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
137 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/curry/cpu/
H A DregCPU.h111 #define R2_REG_BASE 0x003500UL //0x122A00 //sec_r2 macro
129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
130 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
131 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
132 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
133 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
134 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
136 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
137 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/k6/cpu/
H A DregCPU.h111 #define R2_REG_BASE 0x003500UL //0x122A00 //sec_r2 macro
129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
130 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
131 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
132 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
133 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
134 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
136 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
137 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/kano/cpu/
H A DregCPU.h111 #define R2_REG_BASE 0x003500UL //0x122A00 //sec_r2 macro
129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
130 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
131 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
132 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
133 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
134 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
135 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
136 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
137 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/manhattan/cpu/
H A DregCPU.h116 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
156 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
157 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
158 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
159 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
160 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
161 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
162 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
163 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
164 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/macan/cpu/
H A DregCPU.h116 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
156 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
157 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
158 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
159 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
160 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
161 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
162 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
163 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
164 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/maxim/cpu/
H A DregCPU.h123 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
166 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
167 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
168 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
169 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
170 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
171 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
172 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
173 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
174 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/maserati/cpu/
H A DregCPU.h124 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
168 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
169 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
170 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
171 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
172 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
173 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
174 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
175 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
176 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/M7621/cpu/
H A DregCPU.h123 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
166 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
167 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
168 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
169 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
170 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
171 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
172 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
173 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
174 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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/utopia/UTPA2-700.0.x/modules/cpu/hal/M7821/cpu/
H A DregCPU.h124 #define R2_REG_BASE 0x022A00UL //0x122A00 //sec_r2 macro
167 #define R2_REG_STOP (R2_REG_BASE+0x0080UL)
168 #define R2_REG_SDR_LO_INST_BASE (R2_REG_BASE+0x0082UL)
169 #define R2_REG_SDR_HI_INST_BASE (R2_REG_BASE+0x0084UL)
170 #define R2_REG_SDR_LO_DATA_BASE (R2_REG_BASE+0x0086UL)
171 #define R2_REG_SDR_HI_DATA_BASE (R2_REG_BASE+0x0088UL)
172 #define R2_REG_RIU_BASE (R2_REG_BASE+0x008AUL)
173 #define R2_REG_RST_BASE (R2_REG_BASE+0x00B4UL)
174 #define R2_REG_IO1_BASE (R2_REG_BASE+0x00AAUL)
175 #define R2_REG_SPI_BASE (R2_REG_BASE+0x0090UL)
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