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Searched refs:PHASE_OFFSET_LIMIT (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x2000UL) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x2000UL) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x2000UL) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x2000UL) macro
H A Dmhal_xc_chip_config.h.0120 #define PHASE_OFFSET_LIMIT (0x2000UL)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x900UL) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x2000UL) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x400UL) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x400UL) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h120 #define PHASE_OFFSET_LIMIT (0x900UL) macro
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_display.c.03373 MS_U16 u16PhaseLimit = PHASE_OFFSET_LIMIT;
3661 …CResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT]) : (PHASE_OFFSET_LIMIT)))
3665 …rivate->stdrvXC_MVideo_Context.g_bFRCEnabled && (u32NewPhaseDiff < PHASE_OFFSET_LIMIT)) || // FR…
3697 …esourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT]) : (PHASE_OFFSET_LIMIT))) )
4926 … // We set PHASE_OFFSET_LIMIT to "limit for lpll phase offset", the "phase dif value" will take
4927 // PHASE_OFFSET_LIMIT+1 as its max value. then we set the gate to PHASE_OFFSET_LIMIT,
4928 // every case the "phase dif value" is smaller or equal to the PHASE_OFFSET_LIMIT,
4932 …? pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT] : PHASE_OFFSET_LIMIT;
H A Dmdrv_sc_display.c3375 MS_U16 u16PhaseLimit = PHASE_OFFSET_LIMIT; in MDrv_Scaler_SetPhaseLimit()
3663 …CResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT]) : (PHASE_OFFSET_LIMIT))) in MDrv_Scaler_IsPRDLock()
3667 …rivate->stdrvXC_MVideo_Context.g_bFRCEnabled && (u32NewPhaseDiff < PHASE_OFFSET_LIMIT)) || // FR… in MDrv_Scaler_IsPRDLock()
3699 …esourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT]) : (PHASE_OFFSET_LIMIT))) ) in MDrv_Scaler_IsPhaseStable()