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Searched refs:MIU_SC_G1REQUEST_MASK (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_frc.c619 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
624 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
H A Dmhal_sc.c2834 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
2843 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
2851 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c797 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
802 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c780 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
785 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_sc.c1863 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
1869 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
1874 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
1928 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
1933 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h662 #define MIU_SC_G1REQUEST_MASK (0x0E00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h662 #define MIU_SC_G1REQUEST_MASK (0x0E00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_frc.c758 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
763 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
H A Dmhal_sc.c3218 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
3227 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
3235 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_frc.c758 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
763 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in MHal_FRC_set_miusel()
H A Dmhal_sc.c3218 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
3227 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
3235 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h942 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h924 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_sc.c1989 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
1995 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
2000 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
2054 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2059 …MDrv_Write2ByteMask((REG_MIU1_BASE + 0xF2), MIU_SC_G1REQUEST_MASK, MIU_SC_G1REQUEST_MASK); // MIU … in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h990 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h1107 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h1070 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h1127 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h1064 #define MIU_SC_G1REQUEST_MASK (0x0070) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h1132 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h1111 #define MIU_SC_G1REQUEST_MASK (0x0000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_sc.c1320 Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
1325 Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_sc.c1371 Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
1376 Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c2554 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
2563 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
2571 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c2439 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()
2447 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK; in Hal_SC_Enable_MiuMask()

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