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Searched refs:HAL_L1 (Results 1 – 25 of 45) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/mfe/hal/curry/mfe_ex/
H A Dmhal_mfe.c134 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n"); in MHal_MFE_PowerOff()
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level); in MHal_MFE_PowerOff()
246 ms_dprintk(HAL_L1, "Disable clock.\n"); in MHal_MFE_PowerOff()
[all …]
H A Dudma_share.c105 …ms_dprintk(HAL_L1, "MMAPInit: start:0x%x, size:0x%x\n", (unsigned int)buf_base, (unsigned int)buf_… in MMAPInit()
121 …ms_dprintk(HAL_L1, "MMAPMalloc[%s] 0x%x, size = %u\n", msg, (unsigned int)(*ppBufStart), (unsigned… in MMAPMalloc()
140 ms_dprintk(HAL_L1,"memmap:miuPointer: %p\n", memmap->miuPointer); in MMAPMalloc()
141 ms_dprintk(HAL_L1," size: 0x%x\n", (unsigned int)memmap->size); in MMAPMalloc()
142 ms_dprintk(HAL_L1," miuAddress: 0x%x\n", (unsigned int)memmap->miuAddress); in MMAPMalloc()
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7621/mfe_ex/
H A Dmhal_mfe.c134 ms_dprintk(HAL_L1, "HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n"); in MHal_MFE_PowerOff()
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level); in MHal_MFE_PowerOff()
246 ms_dprintk(HAL_L1, "Disable clock.\n"); in MHal_MFE_PowerOff()
[all …]
H A Dudma_share.c105 …ms_dprintk(HAL_L1, "MMAPInit: start:0x%x, size:0x%x\n", (unsigned int)buf_base, (unsigned int)buf_… in MMAPInit()
121 …ms_dprintk(HAL_L1, "MMAPMalloc[%s] 0x%x, size = %u\n", msg, (unsigned int)(*ppBufStart), (unsigned… in MMAPMalloc()
140 ms_dprintk(HAL_L1,"memmap:miuPointer: %p\n", memmap->miuPointer); in MMAPMalloc()
141 ms_dprintk(HAL_L1," size: 0x%x\n", (unsigned int)memmap->size); in MMAPMalloc()
142 ms_dprintk(HAL_L1," miuAddress: 0x%x\n", (unsigned int)memmap->miuAddress); in MMAPMalloc()
/utopia/UTPA2-700.0.x/modules/mfe/hal/maxim/mfe_ex/
H A Dmhal_mfe.c134 ms_dprintk(HAL_L1, "HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n"); in MHal_MFE_PowerOff()
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level); in MHal_MFE_PowerOff()
246 ms_dprintk(HAL_L1, "Disable clock.\n"); in MHal_MFE_PowerOff()
[all …]
H A Dudma_share.c105 …ms_dprintk(HAL_L1, "MMAPInit: start:0x%x, size:0x%x\n", (unsigned int)buf_base, (unsigned int)buf_… in MMAPInit()
121 …ms_dprintk(HAL_L1, "MMAPMalloc[%s] 0x%x, size = %u\n", msg, (unsigned int)(*ppBufStart), (unsigned… in MMAPMalloc()
140 ms_dprintk(HAL_L1,"memmap:miuPointer: %p\n", memmap->miuPointer); in MMAPMalloc()
141 ms_dprintk(HAL_L1," size: 0x%x\n", (unsigned int)memmap->size); in MMAPMalloc()
142 ms_dprintk(HAL_L1," miuAddress: 0x%x\n", (unsigned int)memmap->miuAddress); in MMAPMalloc()
/utopia/UTPA2-700.0.x/modules/mfe/hal/kano/mfe_ex/
H A Dmhal_mfe.c134 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n"); in MHal_MFE_PowerOff()
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level); in MHal_MFE_PowerOff()
246 ms_dprintk(HAL_L1, "Disable clock.\n"); in MHal_MFE_PowerOff()
[all …]
H A Dudma_share.c105 …ms_dprintk(HAL_L1, "MMAPInit: start:0x%x, size:0x%x\n", (unsigned int)buf_base, (unsigned int)buf_… in MMAPInit()
121 …ms_dprintk(HAL_L1, "MMAPMalloc[%s] 0x%x, size = %u\n", msg, (unsigned int)(*ppBufStart), (unsigned… in MMAPMalloc()
140 ms_dprintk(HAL_L1,"memmap:miuPointer: %p\n", memmap->miuPointer); in MMAPMalloc()
141 ms_dprintk(HAL_L1," size: 0x%x\n", (unsigned int)memmap->size); in MMAPMalloc()
142 ms_dprintk(HAL_L1," miuAddress: 0x%x\n", (unsigned int)memmap->miuAddress); in MMAPMalloc()
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7821/mfe_ex/
H A Dmhal_mfe.c134 ms_dprintk(HAL_L1, "HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n"); in MHal_MFE_PowerOff()
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level); in MHal_MFE_PowerOff()
246 ms_dprintk(HAL_L1, "Disable clock.\n"); in MHal_MFE_PowerOff()
[all …]
H A Dudma_share.c105 …ms_dprintk(HAL_L1, "MMAPInit: start:0x%x, size:0x%x\n", (unsigned int)buf_base, (unsigned int)buf_… in MMAPInit()
121 …ms_dprintk(HAL_L1, "MMAPMalloc[%s] 0x%x, size = %u\n", msg, (unsigned int)(*ppBufStart), (unsigned… in MMAPMalloc()
140 ms_dprintk(HAL_L1,"memmap:miuPointer: %p\n", memmap->miuPointer); in MMAPMalloc()
141 ms_dprintk(HAL_L1," size: 0x%x\n", (unsigned int)memmap->size); in MMAPMalloc()
142 ms_dprintk(HAL_L1," miuAddress: 0x%x\n", (unsigned int)memmap->miuAddress); in MMAPMalloc()
/utopia/UTPA2-700.0.x/modules/mfe/hal/maserati/mfe_ex/
H A Dmhal_mfe.c134 ms_dprintk(HAL_L1, "HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n"); in MHal_MFE_PowerOff()
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level); in MHal_MFE_PowerOff()
246 ms_dprintk(HAL_L1, "Disable clock.\n"); in MHal_MFE_PowerOff()
[all …]
H A Dudma_share.c105 …ms_dprintk(HAL_L1, "MMAPInit: start:0x%x, size:0x%x\n", (unsigned int)buf_base, (unsigned int)buf_… in MMAPInit()
121 …ms_dprintk(HAL_L1, "MMAPMalloc[%s] 0x%x, size = %u\n", msg, (unsigned int)(*ppBufStart), (unsigned… in MMAPMalloc()
140 ms_dprintk(HAL_L1,"memmap:miuPointer: %p\n", memmap->miuPointer); in MMAPMalloc()
141 ms_dprintk(HAL_L1," size: 0x%x\n", (unsigned int)memmap->size); in MMAPMalloc()
142 ms_dprintk(HAL_L1," miuAddress: 0x%x\n", (unsigned int)memmap->miuAddress); in MMAPMalloc()
/utopia/UTPA2-700.0.x/modules/mfe/hal/k6/mfe_ex/
H A Dmhal_mfe.c134 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%x\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
174 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
181 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
184 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
186 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
201 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
226 ms_dprintk(HAL_L1, "CLKM disable clock.\n"); in MHal_MFE_PowerOff()
241 ms_dprintk(HAL_L1, "CLKM enable clock level %d.\n", clock_level); in MHal_MFE_PowerOff()
246 ms_dprintk(HAL_L1, "Disable clock.\n"); in MHal_MFE_PowerOff()
[all …]
H A Dudma_share.c105 …ms_dprintk(HAL_L1, "MMAPInit: start:0x%x, size:0x%x\n", (unsigned int)buf_base, (unsigned int)buf_… in MMAPInit()
121 …ms_dprintk(HAL_L1, "MMAPMalloc[%s] 0x%x, size = %u\n", msg, (unsigned int)(*ppBufStart), (unsigned… in MMAPMalloc()
140 ms_dprintk(HAL_L1,"memmap:miuPointer: %p\n", memmap->miuPointer); in MMAPMalloc()
141 ms_dprintk(HAL_L1," size: 0x%x\n", (unsigned int)memmap->size); in MMAPMalloc()
142 ms_dprintk(HAL_L1," miuAddress: 0x%x\n", (unsigned int)memmap->miuAddress); in MMAPMalloc()
/utopia/UTPA2-700.0.x/modules/mfe/hal/maldives/mfe_ex/
H A Dmhal_mfe.c130 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
170 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
173 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
180 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
182 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
197 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
249 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp); in MHal_MFE_SWReset()
276 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits)); in MHal_MFE_GetIRQ()
/utopia/UTPA2-700.0.x/modules/mfe/hal/mustang/mfe_ex/
H A Dmhal_mfe.c130 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
170 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
173 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
180 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
182 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
197 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
249 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp); in MHal_MFE_SWReset()
276 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits)); in MHal_MFE_GetIRQ()
/utopia/UTPA2-700.0.x/modules/mfe/hal/messi/mfe_ex/
H A Dmhal_mfe.c130 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (MS_U32)U32RegBase); in MHAL_MFE_InitRegBase()
170 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
173 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
180 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
182 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
197 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
249 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (MS_U32)temp); in MHal_MFE_SWReset()
276 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (MS_S32)(*irq_bits)); in MHal_MFE_GetIRQ()
/utopia/UTPA2-700.0.x/modules/mfe/hal/manhattan/mfe_ex/
H A Dmhal_mfe.c130 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (MS_U32)U32RegBase); in MHAL_MFE_InitRegBase()
170 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
173 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
180 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
182 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
197 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
249 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (MS_U32)temp); in MHal_MFE_SWReset()
276 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (MS_S32)(*irq_bits)); in MHal_MFE_GetIRQ()
/utopia/UTPA2-700.0.x/modules/mfe/hal/mainz/mfe_ex/
H A Dmhal_mfe.c130 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (MS_U32)U32RegBase); in MHAL_MFE_InitRegBase()
170 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
173 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
180 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
182 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
197 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
249 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (MS_U32)temp); in MHal_MFE_SWReset()
276 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (MS_S32)(*irq_bits)); in MHal_MFE_GetIRQ()
/utopia/UTPA2-700.0.x/modules/mfe/hal/macan/mfe_ex/
H A Dmhal_mfe.c130 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (MS_U32)U32RegBase); in MHAL_MFE_InitRegBase()
170 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
173 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n"); in MHal_MFE_PowerOff()
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
180 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n"); in MHal_MFE_PowerOff()
182 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level); in MHal_MFE_PowerOff()
197 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n"); in MHal_MFE_PowerOff()
249 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (MS_U32)temp); in MHal_MFE_SWReset()
276 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (MS_S32)(*irq_bits)); in MHal_MFE_GetIRQ()
/utopia/UTPA2-700.0.x/modules/mfe/hal/maxim/mfe/Aeon/
H A Dmhal_mfe.c172 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
227 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp); in MHal_MFE_SWReset()
262 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits)); in MHal_MFE_GetIRQ()
325 ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en[0 to 3] = %x %x %x %x\n", \ in MHal_MFE_Enable_MIU_Protection()
334 …ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en = %x\n",mfe_reg.reg_mfe_s_marb_miu_… in MHal_MFE_Enable_MIU_Protection()
418 ms_dprintk(HAL_L1, "TEST_MIU_PROTECTION\n"); in MHal_MFE_Enable_MIU_Protection_Check()
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7821/mfe/Aeon/
H A Dmhal_mfe.c172 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
227 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp); in MHal_MFE_SWReset()
262 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits)); in MHal_MFE_GetIRQ()
325 ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en[0 to 3] = %x %x %x %x\n", \ in MHal_MFE_Enable_MIU_Protection()
334 …ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en = %x\n",mfe_reg.reg_mfe_s_marb_miu_… in MHal_MFE_Enable_MIU_Protection()
418 ms_dprintk(HAL_L1, "TEST_MIU_PROTECTION\n"); in MHal_MFE_Enable_MIU_Protection_Check()
/utopia/UTPA2-700.0.x/modules/mfe/hal/maserati/mfe/Aeon/
H A Dmhal_mfe.c172 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
227 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp); in MHal_MFE_SWReset()
262 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits)); in MHal_MFE_GetIRQ()
325 ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en[0 to 3] = %x %x %x %x\n", \ in MHal_MFE_Enable_MIU_Protection()
334 …ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en = %x\n",mfe_reg.reg_mfe_s_marb_miu_… in MHal_MFE_Enable_MIU_Protection()
418 ms_dprintk(HAL_L1, "TEST_MIU_PROTECTION\n"); in MHal_MFE_Enable_MIU_Protection_Check()
/utopia/UTPA2-700.0.x/modules/mfe/hal/macan/mfe/Aeon/
H A Dmhal_mfe.c172 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
227 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp); in MHal_MFE_SWReset()
262 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits)); in MHal_MFE_GetIRQ()
325 ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en[0 to 3] = %x %x %x %x\n", \ in MHal_MFE_Enable_MIU_Protection()
334 …ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en = %x\n",mfe_reg.reg_mfe_s_marb_miu_… in MHal_MFE_Enable_MIU_Protection()
418 ms_dprintk(HAL_L1, "TEST_MIU_PROTECTION\n"); in MHal_MFE_Enable_MIU_Protection_Check()
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7621/mfe/Aeon/
H A Dmhal_mfe.c172 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase); in MHAL_MFE_InitRegBase()
227 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp); in MHal_MFE_SWReset()
262 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits)); in MHal_MFE_GetIRQ()
325 ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en[0 to 3] = %x %x %x %x\n", \ in MHal_MFE_Enable_MIU_Protection()
334 …ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en = %x\n",mfe_reg.reg_mfe_s_marb_miu_… in MHal_MFE_Enable_MIU_Protection()
418 ms_dprintk(HAL_L1, "TEST_MIU_PROTECTION\n"); in MHal_MFE_Enable_MIU_Protection_Check()

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