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Searched refs:HAL_DMD_RIU_WriteRegBit (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_common.c384 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
842 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
843 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
844 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
845 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
851 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_common.c384 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
842 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
843 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
844 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
845 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
851 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h142 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_common.c384 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
842 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
843 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
844 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
845 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
851 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h142 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_common.c384 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
842 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
843 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
844 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
845 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
851 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_common.c384 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
842 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
843 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
844 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
845 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
851 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_common.c384 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
842 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
843 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
844 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
845 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
851 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h141 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_common.c387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
907 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_common.c386 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
867 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
868 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
873 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
904 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
906 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
907 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
913 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_common.c387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
907 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h161 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_common.c387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
907 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h153 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_common.c388 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
869 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
870 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
876 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
907 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
908 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
909 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
915 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h154 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_common.c387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
907 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h153 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_common.c387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
907 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h153 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_common.c387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
907 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
[all …]
H A DhalDMD_INTERN_common.h153 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_common.c387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_DMD_RIU_WriteRegBit() function
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC in HAL_DMD_ADC_IQ_Switch()
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC in HAL_DMD_ADC_IQ_Switch()
907 … HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap in HAL_DMD_ADC_IQ_Switch()
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q in HAL_DMD_ADC_IQ_Switch()
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC in HAL_DMD_ADC_IQ_Switch()
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H A DhalDMD_INTERN_common.h153 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask);

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