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Searched refs:E_INT_IRQ_0x50_START (Results 1 – 3 of 3) sorted by relevance

/utopia/UTPA2-700.0.x/projects/tmplib/include/
H A DMsIRQ.h221 E_INT_IRQ_0x50_START = 0x50, enumerator
222 E_INT_IRQ_CA_I3 = E_INT_IRQ_0x50_START+0, //U3
223 E_INT_IRQ_HDMI_LEVEL = E_INT_IRQ_0x50_START+1, //U3
224 E_INT_IRQ_MIPS_WADR_ERR = E_INT_IRQ_0x50_START+2, //U3
225 E_INT_IRQ_RASP = E_INT_IRQ_0x50_START+3, //U3
226 E_INT_IRQ_CA_SVP = E_INT_IRQ_0x50_START+4, //U3
227 E_INT_IRQ_UART2MCU = E_INT_IRQ_0x50_START+5, //U3
228 E_INT_IRQ_URDMA2MCU = E_INT_IRQ_0x50_START+6, //U3
229 E_INT_IRQ_IIC1 = E_INT_IRQ_0x50_START+7, //U3
230 E_INT_IRQ_HDCP = E_INT_IRQ_0x50_START+8, //U3
[all …]
/utopia/UTPA2-700.0.x/mxlib/include/
H A DMsIRQ.h221 E_INT_IRQ_0x50_START = 0x50, enumerator
222 E_INT_IRQ_CA_I3 = E_INT_IRQ_0x50_START+0, //U3
223 E_INT_IRQ_HDMI_LEVEL = E_INT_IRQ_0x50_START+1, //U3
224 E_INT_IRQ_MIPS_WADR_ERR = E_INT_IRQ_0x50_START+2, //U3
225 E_INT_IRQ_RASP = E_INT_IRQ_0x50_START+3, //U3
226 E_INT_IRQ_CA_SVP = E_INT_IRQ_0x50_START+4, //U3
227 E_INT_IRQ_UART2MCU = E_INT_IRQ_0x50_START+5, //U3
228 E_INT_IRQ_URDMA2MCU = E_INT_IRQ_0x50_START+6, //U3
229 E_INT_IRQ_IIC1 = E_INT_IRQ_0x50_START+7, //U3
230 E_INT_IRQ_HDCP = E_INT_IRQ_0x50_START+8, //U3
[all …]
/utopia/UTPA2-700.0.x/projects/build/
H A Dpreprocess.txt31364 E_INT_IRQ_0x50_START = 0x50,
31365 E_INT_IRQ_CA_I3 = E_INT_IRQ_0x50_START+0,
31366 E_INT_IRQ_HDMI_LEVEL = E_INT_IRQ_0x50_START+1,
31367 E_INT_IRQ_MIPS_WADR_ERR = E_INT_IRQ_0x50_START+2,
31368 E_INT_IRQ_RASP = E_INT_IRQ_0x50_START+3,
31369 E_INT_IRQ_CA_SVP = E_INT_IRQ_0x50_START+4,
31370 E_INT_IRQ_UART2MCU = E_INT_IRQ_0x50_START+5,
31371 E_INT_IRQ_URDMA2MCU = E_INT_IRQ_0x50_START+6,
31372 E_INT_IRQ_IIC1 = E_INT_IRQ_0x50_START+7,
31373 E_INT_IRQ_HDCP = E_INT_IRQ_0x50_START+8,
[all …]