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Searched refs:CKG_SC1_ODCLK_GATED (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.h223 #define CKG_SC1_ODCLK_GATED BIT(8) macro
H A DhalPNL.c718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.h223 #define CKG_SC1_ODCLK_GATED BIT(8) macro
H A DhalPNL.c718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.h223 #define CKG_SC1_ODCLK_GATED BIT(8) macro
H A DhalPNL.c718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.h223 #define CKG_SC1_ODCLK_GATED BIT(8) macro
H A DhalPNL.c718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h834 #define CKG_SC1_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h840 #define CKG_SC1_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h833 #define CKG_SC1_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h827 #define CKG_SC1_ODCLK_GATED BIT(0) macro
H A Dmhal_xc_chip_config.h.0826 #define CKG_SC1_ODCLK_GATED BIT(0)