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Searched refs:CKG_S2_IDCLK1_XTAL (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h873 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h855 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h919 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c298 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
308 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c255 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
265 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c254 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
264 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c255 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
265 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c254 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
264 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h1034 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h989 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h1046 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h983 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h1051 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h1038 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK macro