| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mdrv_sc_pip.c | 724 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock in MDrv_XC_EnableCLK_for_SUB()
740 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MDrv_XC_EnableCLK_for_SUB()
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| H A D | mdrv_sc_pip.c.0 | 724 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock
740 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
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| H A D | mvideo.c | 484 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MApi_XC_Exit_U2()
527 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MApi_XC_Exit_U2()
567 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock in MApi_XC_Exit_U2()
1120 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock in _MApi_XC_Init_WithoutCreateMutex()
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| H A D | mvideo.c.0 | 481 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
524 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
564 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
1117 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | mhal_xc_chip_config.h | 487 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | mhal_xc_chip_config.h | 487 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 642 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 640 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 655 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 661 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 661 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 663 #define CKG_FICLK_F1_GATED BIT(0) macro
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| H A D | mhal_xc_chip_config.h.0 | 662 #define CKG_FICLK_F1_GATED BIT(0)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 637 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 737 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 697 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 749 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 687 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 754 #define CKG_FICLK_F1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 741 #define CKG_FICLK_F1_GATED BIT(0) macro
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