| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 687 …#define CKG_FCLK_170MHZ (0 << 2) //This is 172M, but driver layer use 170M, to compatiabl… macro
691 #define CKG_FCLK_DEFAULT CKG_FCLK_170MHZ
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| H A D | mhal_xc_chip_config.h.0 | 686 …#define CKG_FCLK_170MHZ (0 << 2) //This is 172M, but driver layer use 170M, to compatiabl…
690 #define CKG_FCLK_DEFAULT CKG_FCLK_170MHZ
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_dip.c | 1529 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1535 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1593 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1601 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
3862 if(u16tmp == CKG_FCLK_170MHZ) in HAL_XC_DIP_Check_Clock()
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/kano/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maserati/pws/ |
| H A D | regCLKGEN.h | 337 #define CKG_FCLK_170MHZ (0UL << 2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | mhal_xc_chip_config.h | 513 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | mhal_xc_chip_config.h | 513 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 668 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 666 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 679 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 685 #define CKG_FCLK_170MHZ (0 << 2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 685 #define CKG_FCLK_170MHZ (0 << 2) macro
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