| /utopia/UTPA2-700.0.x/modules/gpio/hal/k6/gpio/ |
| H A D | halGPIO.c | 125 #define BIT4 BIT(4) macro
267 #define GPIO26_OUT 0x000e4e, BIT4
278 #define GPIO28_IN 0x000496, BIT4
287 #define GPIO30_OUT 0x010718, BIT4
331 #define GPIO39_OEN 0x001423, BIT4
332 #define GPIO39_OUT 0x001424, BIT4
333 #define GPIO39_IN 0x001425, BIT4
337 #define GPIO40_OUT 0x1025ec, BIT4
342 #define GPIO41_OUT 0x1025ee, BIT4
347 #define GPIO42_OUT 0x102556, BIT4
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| /utopia/UTPA2-700.0.x/modules/gpio/hal/k7u/gpio/ |
| H A D | halGPIO.c | 125 #define BIT4 BIT(4) macro
267 #define GPIO26_OUT 0x000e4e, BIT4
278 #define GPIO28_IN 0x000496, BIT4
287 #define GPIO30_OUT 0x010718, BIT4
331 #define GPIO39_OEN 0x001423, BIT4
332 #define GPIO39_OUT 0x001424, BIT4
333 #define GPIO39_IN 0x001425, BIT4
337 #define GPIO40_OUT 0x1025ec, BIT4
342 #define GPIO41_OUT 0x1025ee, BIT4
347 #define GPIO42_OUT 0x102556, BIT4
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| /utopia/UTPA2-700.0.x/modules/gpio/hal/kano/gpio/ |
| H A D | halGPIO.c | 125 #define BIT4 BIT(4) macro
257 #define GPIO24_OUT 0x000e4e, BIT4
268 #define GPIO26_IN 0x000496, BIT4
277 #define GPIO28_OUT 0x010718, BIT4
391 #define GPIO51_OEN 0x001423, BIT4
392 #define GPIO51_OUT 0x001424, BIT4
393 #define GPIO51_IN 0x001425, BIT4
397 #define GPIO52_OUT 0x1025ec, BIT4
402 #define GPIO53_OUT 0x1025ee, BIT4
406 #define GPIO54_OEN 0x102556, BIT4
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| /utopia/UTPA2-700.0.x/modules/gpio/hal/k6lite/gpio/ |
| H A D | halGPIO.c | 125 #define BIT4 BIT(4) macro
381 #define GPIO49_OEN 0x001423, BIT4
382 #define GPIO49_OUT 0x001424, BIT4
383 #define GPIO49_IN 0x001425, BIT4
392 #define GPIO51_OUT 0x1025ec, BIT4
397 #define GPIO52_OUT 0x1025ee, BIT4
402 #define GPIO53_OUT 0x1025a4, BIT4
407 #define GPIO54_OUT 0x1025a6, BIT4
412 #define GPIO55_OUT 0x1025a8, BIT4
417 #define GPIO56_OUT 0x1025aa, BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/gpio/hal/curry/gpio/ |
| H A D | halGPIO.c | 125 #define BIT4 BIT(4) macro
231 #define GPIO19_OEN 0x102556, BIT4
232 #define GPIO19_OUT 0x102556, BIT4
237 #define GPIO20_OUT 0x102558, BIT4
242 #define GPIO21_OUT 0x10255a, BIT4
247 #define GPIO22_OUT 0x10255c, BIT4
252 #define GPIO23_OUT 0x10255e, BIT4
257 #define GPIO24_OUT 0x102560, BIT4
262 #define GPIO25_OUT 0x102562, BIT4
267 #define GPIO26_OUT 0x102564, BIT4
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| /utopia/UTPA2-700.0.x/modules/gpio/hal/maldives/gpio/ |
| H A D | halGPIO.c | 109 #define BIT4 BIT(4) macro
259 #define GPIO26_OUT 0x0e4e, BIT4
285 #define GPIO31_IN 0x0496, BIT4
295 #define GPIO33_IN 0x0497, BIT4
305 #define GPIO35_IN 0x0498, BIT4
315 #define GPIO37_IN 0x0499, BIT4
338 #define GPIO42_OEN 0x1423, BIT4
339 #define GPIO42_OUT 0x1424, BIT4
340 #define GPIO42_IN 0x1425, BIT4
355 #define GPIO45_IN 0x0494, BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/gpio/hal/mustang/gpio/ |
| H A D | halGPIO.c | 109 #define BIT4 BIT(4) macro
259 #define GPIO26_OUT 0x0e4e, BIT4
285 #define GPIO31_IN 0x0496, BIT4
295 #define GPIO33_IN 0x0497, BIT4
305 #define GPIO35_IN 0x0498, BIT4
315 #define GPIO37_IN 0x0499, BIT4
338 #define GPIO42_OEN 0x1423, BIT4
339 #define GPIO42_OUT 0x1424, BIT4
340 #define GPIO42_IN 0x1425, BIT4
355 #define GPIO45_IN 0x0494, BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/ |
| H A D | regMVOP.h | 142 #define VOP_FSYNC_EN BIT4 //frame sync enable
149 #define VOP_OFLD_INV BIT4
156 #define VOP_UV_SWAP BIT4
161 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
180 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
189 #define MFDEC_SRAM_SD_MASK BIT4
200 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
208 #define VOP_FORCELOAD_REG BIT4 //force load registers
221 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1
242 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/ |
| H A D | regMVOP.h | 143 #define VOP_FSYNC_EN BIT4 //frame sync enable
150 #define VOP_OFLD_INV BIT4
157 #define VOP_UV_SWAP BIT4
162 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
181 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
194 #define MFDEC_SRAM_SD_MASK BIT4
205 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
213 #define VOP_FORCELOAD_REG BIT4 //force load registers
226 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1
247 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
[all …]
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/ |
| H A D | regMVOP.h | 142 #define VOP_FSYNC_EN BIT4 //frame sync enable
149 #define VOP_OFLD_INV BIT4
156 #define VOP_UV_SWAP BIT4
161 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
180 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
189 #define MFDEC_SRAM_SD_MASK BIT4
200 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
208 #define VOP_FORCELOAD_REG BIT4 //force load registers
221 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1
242 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/ |
| H A D | regMVOP.h | 142 #define VOP_FSYNC_EN BIT4 //frame sync enable
149 #define VOP_OFLD_INV BIT4
160 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
179 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
188 #define MFDEC_SRAM_SD_MASK BIT4
198 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
206 #define VOP_FORCELOAD_REG BIT4 //force load registers
218 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1
239 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
258 #define VOP_MIU_128BIT BIT4 //MIU bus use 0: 64bit 1:128bit
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/ |
| H A D | regMVOP.h | 140 #define VOP_FSYNC_EN BIT4 //frame sync enable
147 #define VOP_OFLD_INV BIT4
154 #define VOP_UV_SWAP BIT4
159 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
178 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
195 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
203 #define VOP_FORCELOAD_REG BIT4 //force load registers
216 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1
237 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
256 #define VOP_MIU_128BIT BIT4 //MIU bus use 0: 64bit 1:128bit
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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| /utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/ |
| H A D | regCLKGEN.h | 111 #define CKG_MIU_GATED BIT4
133 #define CKG_TCK_GATED BIT4
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
150 #define CKG_STC0_GATED BIT4
159 #define CKG_MAD_STC_GATED BIT4
177 #define CKG_MVD_GATED BIT4
194 #define CKG_DC0_GATED BIT4
218 #define CKG_GE_GATED BIT4
236 #define CKG_GOPG1_GATED BIT4
254 #define CKG_VD_GATED BIT4
[all …]
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