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Searched refs:sw03 (Results 1 – 8 of 8) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu1.c139 p_regs->sw03.dec_axi_wr_id = 0; in hal_m2vd_vdpu1_init_hwcfg()
140 p_regs->sw03.dec_mode = 8; in hal_m2vd_vdpu1_init_hwcfg()
167 p_regs->sw03.dec_mode = 5; in hal_m2vd_vdpu1_gen_regs()
173 p_regs->sw03.dec_mode = 6; in hal_m2vd_vdpu1_gen_regs()
186 p_regs->sw03.pic_interlace_e = 1 - dx->seq_ext.progressive_sequence; in hal_m2vd_vdpu1_gen_regs()
188 p_regs->sw03.pic_fieldmode_e = 0; in hal_m2vd_vdpu1_gen_regs()
190 p_regs->sw03.pic_fieldmode_e = 1; in hal_m2vd_vdpu1_gen_regs()
191 p_regs->sw03.pic_topfield_e = dx->pic_code_ext.picture_structure == 1; in hal_m2vd_vdpu1_gen_regs()
194 p_regs->sw03.pic_b_e = 1; in hal_m2vd_vdpu1_gen_regs()
196 p_regs->sw03.pic_b_e = 0; in hal_m2vd_vdpu1_gen_regs()
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H A Dhal_m2vd_vdpu1_reg.h94 } sw03; member
/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_vdpu1.c55 p_regs->sw03.dec_axi_wr_id = 0; in set_defalut_parameters()
83 p_regs->sw03.rlc_mode_e = 0; in set_regs_parameters()
103 p_regs->sw03.dec_mode = 11; //!< DEC_MODE_AVS in set_regs_parameters()
106 p_regs->sw03.pic_interlace_e = 0; in set_regs_parameters()
107 p_regs->sw03.pic_fieldmode_e = 0; in set_regs_parameters()
108 p_regs->sw03.pic_topfiled_e = 0; in set_regs_parameters()
110 p_regs->sw03.pic_interlace_e = 1; in set_regs_parameters()
111 p_regs->sw03.pic_fieldmode_e = 1; in set_regs_parameters()
112 p_regs->sw03.pic_topfiled_e = p_hal->first_field; in set_regs_parameters()
119 p_regs->sw03.pic_b_e = 1; in set_regs_parameters()
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H A Dhal_avsd_plus.c64 p_regs->sw03.dec_axi_wr_id = 0; in set_defalut_parameters()
107 p_regs->sw03.dec_mode = 11; //!< DEC_MODE_AVS in set_regs_parameters()
110 p_regs->sw03.pic_interlace_e = 0; in set_regs_parameters()
111 p_regs->sw03.pic_fieldmode_e = 0; in set_regs_parameters()
112 p_regs->sw03.pic_topfiled_e = 0; in set_regs_parameters()
114 p_regs->sw03.pic_interlace_e = 1; in set_regs_parameters()
115 p_regs->sw03.pic_fieldmode_e = 1; in set_regs_parameters()
117 p_regs->sw03.pic_topfiled_e = p_hal->first_field; in set_regs_parameters()
119 p_regs->sw03.pic_topfiled_e = !p_hal->first_field; in set_regs_parameters()
127 p_regs->sw03.pic_b_e = 1; in set_regs_parameters()
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H A Dhal_avsd_vdpu1_reg.h93 } sw03; member
H A Dhal_avsd_plus_reg.h91 } sw03; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_rkv_reg.c445 p_regs->sw03.slice_num_lowbits = 0x7ff; in set_registers()
446 p_regs->sw03.slice_num_highbit = 1; in set_registers()
468 p_regs->sw03.y_hor_virstride = hor_virstride / 16; in set_registers()
469 p_regs->sw03.uv_hor_virstride = hor_virstride / 16; in set_registers()
H A Dhal_h264d_rkv_reg.h91 } sw03; member