139     p_regs->sw03.dec_axi_wr_id = 0;  in hal_m2vd_vdpu1_init_hwcfg()
140     p_regs->sw03.dec_mode = 8;  in hal_m2vd_vdpu1_init_hwcfg()
167             p_regs->sw03.dec_mode = 5;  in hal_m2vd_vdpu1_gen_regs()
173             p_regs->sw03.dec_mode = 6;  in hal_m2vd_vdpu1_gen_regs()
186         p_regs->sw03.pic_interlace_e = 1 - dx->seq_ext.progressive_sequence;  in hal_m2vd_vdpu1_gen_regs()
188             p_regs->sw03.pic_fieldmode_e = 0;  in hal_m2vd_vdpu1_gen_regs()
190             p_regs->sw03.pic_fieldmode_e = 1;  in hal_m2vd_vdpu1_gen_regs()
191             p_regs->sw03.pic_topfield_e = dx->pic_code_ext.picture_structure == 1;  in hal_m2vd_vdpu1_gen_regs()
194             p_regs->sw03.pic_b_e = 1;  in hal_m2vd_vdpu1_gen_regs()
196             p_regs->sw03.pic_b_e = 0;  in hal_m2vd_vdpu1_gen_regs()
198             p_regs->sw03.pic_inter_e = 0;  in hal_m2vd_vdpu1_gen_regs()
200             p_regs->sw03.pic_inter_e = 1;  in hal_m2vd_vdpu1_gen_regs()
203         p_regs->sw03.fwd_interlace_e = 0;  in hal_m2vd_vdpu1_gen_regs()
204         p_regs->sw03.write_mvs_e = 0;  in hal_m2vd_vdpu1_gen_regs()
247         p_regs->sw03.dec_out_dis = 0;  in hal_m2vd_vdpu1_gen_regs()
248         p_regs->sw03.filtering_dis = 1;  in hal_m2vd_vdpu1_gen_regs()