| /rockchip-linux_mpp/mpp/hal/rkenc/jpege/ |
| H A D | hal_jpege_vepu511_reg.h | 74 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_jpege_vpu720_reg.h | 227 RK_U32 pic_wd8_m1 : 13; member
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| H A D | hal_jpege_vepu540c_reg.h | 460 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_jpege_vpu720.c | 468 reg_base->reg029_sw_enc_rsl.pic_wd8_m1 = encode_width / 8 - 1; in hal_jpege_vpu720_gen_regs()
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| H A D | hal_jpege_vepu511.c | 220 regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in vepu511_set_jpeg_reg()
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| /rockchip-linux_mpp/mpp/hal/rkenc/common/ |
| H A D | vepu540c_common.c | 184 regs->reg0272_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in vepu540c_set_jpeg_reg()
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| H A D | vepu540c_common.h | 567 RK_U32 pic_wd8_m1 : 11; member
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| H A D | vepu510_common.h | 540 RK_U32 pic_wd8_m1 : 11; member
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| H A D | vepu511_common.h | 869 RK_U32 pic_wd8_m1 : 11; member
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| /rockchip-linux_mpp/mpp/hal/rkenc/h265e/ |
| H A D | hal_h265e_vepu541_reg.h | 131 RK_U32 pic_wd8_m1 : 9; member
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| H A D | hal_h265e_vepu540c_reg.h | 467 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_h265e_vepu511_reg.h | 380 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_h265e_vepu540c.c | 958 RK_S32 pic_wdt_align = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 31) / 32 ; in vepu540c_h265_set_me_regs()
1261 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v540c_gen_regs()
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| H A D | hal_h265e_vepu541.c | 1332 pic_cime_temp = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in vepu540_h265_set_me_ram()
1539 regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v541_gen_regs()
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| H A D | hal_h265e_vepu580_reg.h | 350 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_h265e_vepu580.c | 268 RK_U32 pic_wd64 = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64; in vepu580_h265_set_me_ram()
2742 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v580_gen_regs()
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| /rockchip-linux_mpp/mpp/hal/rkenc/h264e/ |
| H A D | hal_h264e_vepu541_reg.h | 248 RK_U32 pic_wd8_m1 : 9; member
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| H A D | hal_h264e_vepu540c_reg.h | 379 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_h264e_vepu511_reg.h | 233 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_h264e_vepu541.c | 466 regs->reg012.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu541_prep()
1309 RK_U32 pic_temp = ((regs->reg012.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in setup_vepu541_me()
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| H A D | hal_h264e_vepu540c.c | 469 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu540c_prep()
1167 RK_S32 pic_wdt_align = ((base_regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 2; in calc_cime_parameter()
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| H A D | hal_h264e_vepu580_reg.h | 357 RK_U32 pic_wd8_m1 : 11; member
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| H A D | hal_h264e_vepu580.c | 718 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()
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| H A D | hal_h264e_vepu510.c | 715 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu510_prep()
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| H A D | hal_h264e_vepu511.c | 714 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu511_prep()
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