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Searched refs:SwReg02 (Results 1 – 6 of 6) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu1.c198 regs->SwReg02.sw_dec_out_endian = 1; in hal_vpu1_h263d_gen_regs()
199 regs->SwReg02.sw_dec_in_endian = 1; in hal_vpu1_h263d_gen_regs()
200 regs->SwReg02.sw_dec_inswap32_e = 1; in hal_vpu1_h263d_gen_regs()
201 regs->SwReg02.sw_dec_outswap32_e = 1; in hal_vpu1_h263d_gen_regs()
202 regs->SwReg02.sw_dec_strswap32_e = 1; in hal_vpu1_h263d_gen_regs()
203 regs->SwReg02.sw_dec_strendian_e = 1; in hal_vpu1_h263d_gen_regs()
204 regs->SwReg02.sw_dec_max_burst = 16; in hal_vpu1_h263d_gen_regs()
206 regs->SwReg02.sw_dec_timeout_e = 1; in hal_vpu1_h263d_gen_regs()
207 regs->SwReg02.sw_dec_clk_gate_e = 1; in hal_vpu1_h263d_gen_regs()
H A Dhal_h263d_vdpu1_reg.h63 } SwReg02; member
/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_vdpu1.c358 regs->SwReg02.sw_dec_out_endian = 1; in vdpu1_mpg4d_gen_regs()
359 regs->SwReg02.sw_dec_in_endian = 1; in vdpu1_mpg4d_gen_regs()
360 regs->SwReg02.sw_dec_inswap32_e = 1; in vdpu1_mpg4d_gen_regs()
361 regs->SwReg02.sw_dec_outswap32_e = 1; in vdpu1_mpg4d_gen_regs()
362 regs->SwReg02.sw_dec_strswap32_e = 1; in vdpu1_mpg4d_gen_regs()
363 regs->SwReg02.sw_dec_strendian_e = 1; in vdpu1_mpg4d_gen_regs()
364 regs->SwReg02.sw_dec_max_burst = 16; in vdpu1_mpg4d_gen_regs()
366 regs->SwReg02.sw_dec_timeout_e = 1; in vdpu1_mpg4d_gen_regs()
367 regs->SwReg02.sw_dec_clk_gate_e = 1; in vdpu1_mpg4d_gen_regs()
H A Dhal_m4vd_vdpu1_reg.h64 } SwReg02; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu1.c692 p_reg->SwReg02.sw_dec_out_endian = 1; /* little endian */ in vdpu1_set_device_regs()
693 p_reg->SwReg02.sw_dec_in_endian = 0; /* big endian */ in vdpu1_set_device_regs()
694 p_reg->SwReg02.sw_dec_strendian_e = 1; //!< little endian in vdpu1_set_device_regs()
695 p_reg->SwReg02.sw_tiled_mode_msb = 0; /* 0: raster scan 1: tiled */ in vdpu1_set_device_regs()
698 p_reg->SwReg02.sw_dec_max_burst = 16; /* (0, 4, 8, 16) choice one */ in vdpu1_set_device_regs()
699 p_reg->SwReg02.sw_dec_scmd_dis = 0; /* disable */ in vdpu1_set_device_regs()
700 p_reg->SwReg02.sw_dec_adv_pre_dis = 0; /* disable */ in vdpu1_set_device_regs()
702 p_reg->SwReg02.sw_dec_latency = 0; /* compensation for bus latency; values up to 63 */ in vdpu1_set_device_regs()
703 p_reg->SwReg02.sw_dec_data_disc_e = 0; in vdpu1_set_device_regs()
704 p_reg->SwReg02.sw_dec_out_endian = 1; /* little endian */ in vdpu1_set_device_regs()
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H A Dhal_h264d_vdpu1_reg.h65 } SwReg02; member