692     p_reg->SwReg02.sw_dec_out_endian = 1;  /* little endian */  in vdpu1_set_device_regs()
693     p_reg->SwReg02.sw_dec_in_endian = 0;  /* big endian */  in vdpu1_set_device_regs()
694     p_reg->SwReg02.sw_dec_strendian_e = 1; //!< little endian  in vdpu1_set_device_regs()
695     p_reg->SwReg02.sw_tiled_mode_msb = 0; /* 0: raster scan  1: tiled */  in vdpu1_set_device_regs()
698     p_reg->SwReg02.sw_dec_max_burst = 16; /* (0, 4, 8, 16) choice one */  in vdpu1_set_device_regs()
699     p_reg->SwReg02.sw_dec_scmd_dis = 0; /* disable */  in vdpu1_set_device_regs()
700     p_reg->SwReg02.sw_dec_adv_pre_dis = 0; /* disable */  in vdpu1_set_device_regs()
702     p_reg->SwReg02.sw_dec_latency = 0; /* compensation for bus latency; values up to 63 */  in vdpu1_set_device_regs()
703     p_reg->SwReg02.sw_dec_data_disc_e = 0;  in vdpu1_set_device_regs()
704     p_reg->SwReg02.sw_dec_out_endian = 1; /* little endian */  in vdpu1_set_device_regs()
705     p_reg->SwReg02.sw_dec_inswap32_e = 1; /* little endian */  in vdpu1_set_device_regs()
706     p_reg->SwReg02.sw_dec_outswap32_e = 1;  in vdpu1_set_device_regs()
707     p_reg->SwReg02.sw_dec_strswap32_e = 1;  in vdpu1_set_device_regs()
708     p_reg->SwReg02.sw_dec_strendian_e = 1; /* little endian */  in vdpu1_set_device_regs()
709     p_reg->SwReg02.sw_dec_timeout_e = 1;  in vdpu1_set_device_regs()
712     p_reg->SwReg02.sw_dec_clk_gate_e = 1;  in vdpu1_set_device_regs()
716     p_reg->SwReg02.sw_dec_axi_rd_id = (0xFF & 0xFFU); /* 0-255 */  in vdpu1_set_device_regs()