| /rk3399_rockchip-uboot/arch/arm/mach-tegra/ |
| H A D | cpu.c | 56 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
57 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
58 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
59 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
74 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
75 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
76 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
77 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
[all …]
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| H A D | clock.c | 91 u32 *divp, u32 *cpcon, u32 *lfcon) in clock_ll_read_pll() argument
108 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; in clock_ll_read_pll()
115 u32 divp, u32 cpcon, u32 lfcon) in clock_start_pll() argument
144 misc_data |= cpcon << pllinfo->kcp_shift; in clock_start_pll()
589 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) in clock_set_rate() argument
629 misc_reg |= cpcon << pllinfo->kcp_shift; in clock_set_rate()
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| H A D | cpu.h | 64 u8 cpcon; member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 63 u32 divp, u32 cpcon, u32 lfcon);
90 u32 *divp, u32 *cpcon, u32 *lfcon);
372 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
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| H A D | warmboot.h | 91 u32 cpcon:4; member
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot.c | 154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
157 &cpcon, &lfcon)) in warmboot_save_sdram_params()
162 scratch2.pllm_misc_cpcon = cpcon; in warmboot_save_sdram_params()
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| H A D | warmboot_avp.c | 186 pllx_misc.cpcon = scratch3.pllx_misc_cpcon; in wb_start()
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 964 unsigned int m = 1, n = 200, cpcon = 13; in tegra_plle_enable() local
998 value |= PLLE_BASE_PLDIV_CML(cpcon); in tegra_plle_enable()
1067 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1113 cpcon = 2; in clock_set_display_rate()
1115 cpcon = 3; in clock_set_display_rate()
1117 cpcon = 8; in clock_set_display_rate()
1119 cpcon = 12; in clock_set_display_rate()
1128 __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon); in clock_set_display_rate()
1133 clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon); in clock_set_display_rate()
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 708 unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000; in tegra_plle_enable() local
738 value |= PLLE_BASE_PLDIV_CML(cpcon); in tegra_plle_enable()
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