Searched refs:bus_index (Results 1 – 2 of 2) sorted by relevance
96 u32 bus_index, global_bus; in ddr3_tip_static_round_trip_arr_build() local115 for (bus_index = 0; bus_index < bus_per_interface; in ddr3_tip_static_round_trip_arr_build()116 bus_index++) { in ddr3_tip_static_round_trip_arr_build()117 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_static_round_trip_arr_build()118 global_bus = (if_id * bus_per_interface) + bus_index; in ddr3_tip_static_round_trip_arr_build()153 u32 bus_index; /* index to the bus loop */ in ddr3_tip_write_leveling_static_config() local169 for (bus_index = bus_start_index; in ddr3_tip_write_leveling_static_config()170 bus_index < (bus_start_index + bus_per_interface); bus_index++) { in ddr3_tip_write_leveling_static_config()171 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_write_leveling_static_config()172 phase = round_trip_delay_arr[bus_index] / (32 * adll_period); in ddr3_tip_write_leveling_static_config()[all …]
307 mem_mask = 0, bus_index = 0; in hws_ddr3_tip_init_controller() local334 for (bus_index = 0; in hws_ddr3_tip_init_controller()335 bus_index < GET_TOPOLOGY_NUM_OF_BUSES(); in hws_ddr3_tip_init_controller()336 bus_index++) { in hws_ddr3_tip_init_controller()337 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in hws_ddr3_tip_init_controller()340 as_bus_params[bus_index].mirror_enable_bitmask; in hws_ddr3_tip_init_controller()988 u32 bus_index = 0; in ddr3_tip_bus_read() local993 for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_bus_read()994 bus_index++) { in ddr3_tip_bus_read()995 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_bus_read()[all …]