96 	u32 bus_index, global_bus;  in ddr3_tip_static_round_trip_arr_build()  local
115 		for (bus_index = 0; bus_index < bus_per_interface;  in ddr3_tip_static_round_trip_arr_build()
116 		     bus_index++) {  in ddr3_tip_static_round_trip_arr_build()
117 			VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in ddr3_tip_static_round_trip_arr_build()
118 			global_bus = (if_id * bus_per_interface) + bus_index;  in ddr3_tip_static_round_trip_arr_build()
153 	u32 bus_index;		/* index to the bus loop */  in ddr3_tip_write_leveling_static_config()  local
169 	for (bus_index = bus_start_index;  in ddr3_tip_write_leveling_static_config()
170 	     bus_index < (bus_start_index + bus_per_interface); bus_index++) {  in ddr3_tip_write_leveling_static_config()
171 		VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in ddr3_tip_write_leveling_static_config()
172 		phase = round_trip_delay_arr[bus_index] / (32 * adll_period);  in ddr3_tip_write_leveling_static_config()
173 		adll = (round_trip_delay_arr[bus_index] -  in ddr3_tip_write_leveling_static_config()
183 					  bus_index, phase, adll));  in ddr3_tip_write_leveling_static_config()
190 			      (bus_index % 4), DDR_PHY_DATA,  in ddr3_tip_write_leveling_static_config()
195 			      ACCESS_TYPE_UNICAST, (bus_index % 4),  in ddr3_tip_write_leveling_static_config()
212 	u32 bus_index;		/* index to the bus loop */  in ddr3_tip_read_leveling_static_config()  local
252 	for (bus_index = bus_start_index;  in ddr3_tip_read_leveling_static_config()
253 	     bus_index < (bus_start_index + bus_per_interface);  in ddr3_tip_read_leveling_static_config()
254 	     bus_index += 2) {  in ddr3_tip_read_leveling_static_config()
255 		VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in ddr3_tip_read_leveling_static_config()
258 				(bus_index % 4)].cs_bitmask].cs_num;  in ddr3_tip_read_leveling_static_config()
261 		min_delay = (total_round_trip_delay_arr[bus_index] <  in ddr3_tip_read_leveling_static_config()
262 			     total_round_trip_delay_arr[bus_index + 1]) ?  in ddr3_tip_read_leveling_static_config()
263 			total_round_trip_delay_arr[bus_index] :  in ddr3_tip_read_leveling_static_config()
264 			total_round_trip_delay_arr[bus_index + 1];  in ddr3_tip_read_leveling_static_config()
270 			 bus_index, min_delay, cs, rd_sample_dly[cs]));  in ddr3_tip_read_leveling_static_config()
273 		phase0 = (total_round_trip_delay_arr[bus_index] -  in ddr3_tip_read_leveling_static_config()
275 		phase1 = (total_round_trip_delay_arr[bus_index + 1] -  in ddr3_tip_read_leveling_static_config()
284 		adll0 = (u32)((total_round_trip_delay_arr[bus_index] -  in ddr3_tip_read_leveling_static_config()
288 		adll1 = (u32)((total_round_trip_delay_arr[bus_index + 1] -  in ddr3_tip_read_leveling_static_config()
310 			      (bus_index % 4), DDR_PHY_DATA, PHY_READ_DELAY(cs),  in ddr3_tip_read_leveling_static_config()
314 			      ((bus_index + 1) % 4), DDR_PHY_DATA,  in ddr3_tip_read_leveling_static_config()
318 	for (bus_index = 0; bus_index < bus_per_interface; bus_index++) {  in ddr3_tip_read_leveling_static_config()
319 		VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in ddr3_tip_read_leveling_static_config()
322 			      bus_index, DDR_PHY_DATA, 0x3, data3, 0x1f));  in ddr3_tip_read_leveling_static_config()