307 		mem_mask = 0, bus_index = 0;  in hws_ddr3_tip_init_controller()  local
334 			for (bus_index = 0;  in hws_ddr3_tip_init_controller()
335 			     bus_index < GET_TOPOLOGY_NUM_OF_BUSES();  in hws_ddr3_tip_init_controller()
336 			     bus_index++) {  in hws_ddr3_tip_init_controller()
337 				VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in hws_ddr3_tip_init_controller()
340 					as_bus_params[bus_index].mirror_enable_bitmask;  in hws_ddr3_tip_init_controller()
988 	u32 bus_index = 0;  in ddr3_tip_bus_read()  local
993 		for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();  in ddr3_tip_bus_read()
994 		     bus_index++) {  in ddr3_tip_bus_read()
995 			VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in ddr3_tip_bus_read()
999 				      bus_index, phy_type, reg_addr, 0,  in ddr3_tip_bus_read()
1005 			data[bus_index] = (data_read[if_id] & 0xffff);  in ddr3_tip_bus_read()
1228 	u32 bus_index = 0;  in ddr3_tip_freq_set()  local
1302 		for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();  in ddr3_tip_freq_set()
1303 		     bus_index++) {  in ddr3_tip_freq_set()
1304 			VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in ddr3_tip_freq_set()
1307 				as_bus_params[bus_index].mirror_enable_bitmask;  in ddr3_tip_freq_set()
2434 	u32 if_id = 0, mem_mask = 0, bus_index = 0;  in ddr3_tip_enable_init_sequence()  local
2456 		for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES();  in ddr3_tip_enable_init_sequence()
2457 		     bus_index++) {  in ddr3_tip_enable_init_sequence()
2458 			VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);  in ddr3_tip_enable_init_sequence()
2461 				as_bus_params[bus_index].mirror_enable_bitmask;  in ddr3_tip_enable_init_sequence()