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Searched refs:SGRF_SYS_BASE (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1103b/
H A Drv1103b.c46 #define SGRF_SYS_BASE 0x20250000 macro
140 writel(entry_point, SGRF_SYS_BASE + SGRF_SYS_HPMCU_BOOT_DDR); in spl_fit_standalone_release()
166 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON0); in arch_cpu_init()
167 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON1); in arch_cpu_init()
168 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON2); in arch_cpu_init()
169 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON3); in arch_cpu_init()
170 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON4); in arch_cpu_init()
171 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON5); in arch_cpu_init()
172 writel(0x01f00000, SGRF_SYS_BASE + FIREWALL_CON7); in arch_cpu_init()
174 writel(0x00020000, SGRF_SYS_BASE + SGRF_SYS_OTP_CON); in arch_cpu_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1126b/
H A Drv1126b.c110 #define SGRF_SYS_BASE 0x20220000 macro
341 writel(entry_point, SGRF_SYS_BASE + SGRF_HPMCU_BOOT_ADDR); in spl_fit_standalone_release()
342 writel(0x1 << 20, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); in spl_fit_standalone_release()
362 writel(0x10000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); in arch_cpu_init()
364 writel(0x20000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); in arch_cpu_init()
366 writel(0x40000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); in arch_cpu_init()
368 writel(0x80000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); in arch_cpu_init()
370 writel(0x80038000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0); in arch_cpu_init()
372 writel(0xC00000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0); in arch_cpu_init()
375 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON0); in arch_cpu_init()
[all …]