1 /*
2 * Copyright (c) 2025 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <misc.h>
9 #include <mmc.h>
10 #include <spl.h>
11 #include <image.h>
12 #include <bidram.h>
13 #include <asm/io.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/grf_rv1126b.h>
17 #include <asm/arch/ioc_rv1126b.h>
18 #include <asm/arch/rk_atags.h>
19 #include <asm/arch/param.h>
20 #include <asm/arch/rockchip_smccc.h>
21 #include <asm/system.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* CRU */
26 #define CRU_BUS_BASE 0x20010000
27 #define CRU_BUS_GATE_CON06 0x818
28 #define CRU_BUS_SOFTRST_CON01 0x0a04
29 #define CRU_PMU_BASE 0x20040000
30 #define CRU_PMU_SOFTRST_CON03 0x0a0c
31 #define PERI_CRU_BASE 0x20020000
32 #define PERICRU_PERI_SOFTRST_CON01 0x0a04
33
34 /* GRF */
35 #define SYS_GRF_BASE 0x20100000
36 #define TSADC_GRF_CON0 0x50
37 #define TSADC_GRF_CON1 0x54
38 #define TSADC_GRF_CON6 0x68
39 #define TSADC_GRF_ST1 0x114
40 #define TSADC_DEF_WIDTH 0x00010001
41 #define TSADC_TARGET_WIDTH 24000
42 #define TSADC_DEF_BIAS 32
43 #define TSADC_MIN_BIAS 0x1
44 #define TSADC_MAX_BIAS 0x7f
45 #define TSADC_UNLOCK_VALUE 0xa5
46 #define TSADC_UNLOCK_VALUE_MASK (0xff << 16)
47 #define TSADC_UNLOCK_TRIGGER BIT(8)
48 #define TSADC_UNLOCK_TRIGGER_MASK (BIT(8) << 16)
49 #define GRF_JTAG_CON0 0x904
50
51 #define PERI_GRF_BASE 0x20110000
52 #define PERI_GRF_USB2HOSTPHY_CON0 0x001c
53 #define PERI_GRF_USB3DRD_CON1 0x003C
54
55 #define VI_GRF_BASE 0x20150000
56 #define SARADC1_GRF_CON0 0x80
57 #define SARADC2_GRF_CON0 0x90
58
59 #define VEPU_GRF_BASE 0x20160000
60 #define SARADC0_GRF_CON0 0x0C
61
62 /* PMU */
63 #define PMU_GRF_BASE 0x20130000
64 #define PMU_GRF_SOC_CON0 0x0000
65 #define PMU2_BASE 0x20838000
66 #define PMU2_PWR_GATE_SFTCON0 0x0210
67
68 /* GPIO/IOC */
69 #define GPIO0_BASE 0x20600000
70 #define GPIO_SWPORT_DR_L 0x00
71 #define GPIO_SWPORT_DDR_L 0x08
72
73 #define PMUIO0_IOC_BASE 0x201a0000
74 #define GPIO0A_IOMUX_SEL_L 0x0
75 #define GPIO0A_IOMUX_SEL_H 0x4
76 #define GPIO0B_IOMUX_SEL_L 0x8
77
78 #define VCCIO1_IOC_BASE 0x201b0000
79 #define GPIO1A_IOMUX_SEL_L 0x20
80 #define GPIO1A_IOMUX_SEL_H 0x24
81 #define GPIO1B_IOMUX_SEL_L 0x28
82 #define GPIO1B_IOMUX_SEL_H 0x2c
83 #define GPIO1_IOC_IO1_VSEL 0x908
84 #define VCCIO1_VD_3V3 BIT(15)
85 #define GPIO1_IOC_GPIO1B_DS_0 0x150
86 #define GPIO1_IOC_GPIO1B_DS_1 0x154
87 #define GPIO1_IOC_GPIO1B_DS_2 0x158
88 #define GPIO1_IOC_GPIO1B_DS_3 0x15c
89
90 #define VCCIO2_IOC_BASE 0x201b8000
91 #define GPIO2A_IOMUX_SEL_L 0x40
92 #define GPIO2A_IOMUX_SEL_H 0x44
93 #define GPIO2A_PULL 0x320
94
95 #define VCCIO3_IOC_BASE 0x201c0000
96 #define GPIO3A_IOMUX_SEL_L 0x60
97 #define GPIO3A_IOMUX_SEL_H 0x64
98 #define GPIO3B_IOMUX_SEL_H 0x6c
99 #define GPIO3A_PULL 0x330
100
101 #define VCCIO6_IOC_BASE 0x201D8000
102 #define GPIO6C_PULL 0x368
103 #define GPIO6C_IE 0x468
104 #define GPIO6C_SMT 0x568
105
106 #define VCCIO7_IOC_BASE 0x201E0000
107 #define GRF_DSM_IOC_CON0 0x0ca0
108
109 /* SGRF/FIREWALL */
110 #define SGRF_SYS_BASE 0x20220000
111 #define SGRF_HPMCU_BOOT_ADDR 0x0c
112 #define SGRF_SYS_AHB_SECURE_SGRF_CON 0x14
113 #define SGRF_SYS_AXI_SECURE_SGRF_CON0 0x18
114 #define FIREWALL_SLV_CON0 0x20
115 #define FIREWALL_SLV_CON1 0x24
116 #define FIREWALL_SLV_CON2 0x28
117 #define FIREWALL_SLV_CON3 0x2c
118 #define FIREWALL_SLV_CON4 0x30
119 #define FIREWALL_SLV_CON5 0x34
120 #define OTP_SGRF_CON 0x1c
121
122 #define SGRF_PMU_BASE 0x20230000
123 #define SGRF_PMU_SOC_CON0 0x00
124 #define SGRF_PMU_SOC_CON1 0x04
125 #define SGRF_LPMCU_BOOT_ADDR 0x20
126
127 #define PVTPLL_ISP_BASE 0x21C60000
128 #define PVTPLL_ENC_BASE 0x21F00000
129 #define PVTPLL_AIISP_BASE 0x21FC0000
130 #define PVTPLL_GCK_CFG 0x20
131 #define PVTPLL_GCK_LEN 0x24
132
133 #ifdef CONFIG_ARM64
134 #include <asm/armv8/mmu.h>
135
136 static struct mm_region rv1126b_mem_map[] = {
137 {
138 .virt = 0x00010000UL,
139 .phys = 0x00010000UL,
140 .size = 0x0fff0000UL,
141 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
142 PTE_BLOCK_INNER_SHARE
143 }, {
144 .virt = 0x20000000UL,
145 .phys = 0x20000000UL,
146 .size = 0x02800000UL,
147 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
148 PTE_BLOCK_NON_SHARE |
149 PTE_BLOCK_PXN | PTE_BLOCK_UXN
150 }, {
151 .virt = 0x3ff1e000UL,
152 .phys = 0x3ff1e000UL,
153 .size = 0x000e2000UL,
154 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
155 PTE_BLOCK_NON_SHARE |
156 PTE_BLOCK_PXN | PTE_BLOCK_UXN
157 }, {
158 .virt = 0x40000000UL,
159 .phys = 0x40000000UL,
160 .size = 0x100000000UL - 0x40000000UL,
161 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
162 PTE_BLOCK_INNER_SHARE
163 }, {
164 /* List terminator */
165 0,
166 }
167 };
168
169 struct mm_region *mem_map = rv1126b_mem_map;
170 #endif
171
board_debug_uart_init(void)172 void board_debug_uart_init(void)
173 {
174 /* No need to change uart in most time. */
175 }
176
board_set_iomux(enum if_type if_type,int devnum,int routing)177 void board_set_iomux(enum if_type if_type, int devnum, int routing)
178 {
179 switch (if_type) {
180 case IF_TYPE_MMC:
181 if (devnum == 0) {
182 writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
183 writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
184 writel(0xf0f01010, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
185 } else if (devnum == 1) {
186 #if CONFIG_SPL_BUILD
187 /* set SDMMC D0-3/CMD/CLK to gpio and pull down */
188 writel(0xffff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L);
189 writel(0x00ff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H);
190 writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
191 writel(0x0fff0aaa, VCCIO2_IOC_BASE + GPIO2A_PULL);
192
193 /* SDMMC PWREN GPIO0A4 power down and power up */
194 writel(0x01000100, GPIO0_BASE + GPIO_SWPORT_DR_L);
195 writel(0x01000100, GPIO0_BASE + GPIO_SWPORT_DDR_L);
196 mdelay(50);
197 writel(0x01000000, GPIO0_BASE + GPIO_SWPORT_DR_L);
198 #endif
199 /* set SDMMC D0-3/CMD/CLK and pull up */
200 writel(0xffff1111, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L);
201 writel(0x00ff0011, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H);
202 writel(0x00f00010, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
203 writel(0x0fff0555, VCCIO2_IOC_BASE + GPIO2A_PULL);
204 } else if (devnum == 2) {
205 writel(0xffff1111, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L);
206 writel(0x00ff0011, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H);
207 writel(0x0f000300, VCCIO3_IOC_BASE + GPIO3B_IOMUX_SEL_H);
208 /* Pull up */
209 writel(0x0ffc0554, VCCIO2_IOC_BASE + GPIO3A_PULL);
210 }
211 break;
212 case IF_TYPE_MTD:
213 if (routing == 0) {
214 /* FSPI0 M0 */
215 writel(0x0f0f0101, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
216 writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_H);
217 writel(0x00f00020, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
218 } else if (routing == 1) {
219 /* FSPI1 M0 */
220 writel(0x0fff0111, PMUIO0_IOC_BASE + GPIO0B_IOMUX_SEL_L);
221 writel(0xff001100, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
222 writel(0x00f00010, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_L);
223 } else if (routing == 2) {
224 /* FSPI1 M1 */
225 writel(0xffff2222, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
226 writel(0xf0f02020, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
227 }
228 break;
229 default:
230 printf("Bootdev 0x%x is not support\n", if_type);
231 }
232 }
233
board_unset_iomux(enum if_type if_type,int devnum,int routing)234 void board_unset_iomux(enum if_type if_type, int devnum, int routing)
235 {
236 switch (if_type) {
237 case IF_TYPE_MMC:
238 if (devnum == 0) {
239 writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
240 writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
241 writel(0xf0f00000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
242 } else if (devnum == 1) {
243 /* SDMMC0_D2,D3 -> JTAG_TMS_M1, JTAG_TCK_M1 */
244 writel(0xffff4400, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L);
245 /* Other SDMMC0 PINS -> GPIO */
246 writel(0x00ff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H);
247 writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
248 /* Pull down */
249 writel(0x0fff0aaa, VCCIO2_IOC_BASE + GPIO2A_PULL);
250 } else if (devnum == 2) {
251 writel(0xffff0000, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L);
252 writel(0x00ff0000, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H);
253 writel(0x0f000000, VCCIO3_IOC_BASE + GPIO3B_IOMUX_SEL_H);
254 /* Pull down */
255 writel(0x0ffc0000, VCCIO2_IOC_BASE + GPIO3A_PULL);
256 }
257 break;
258 case IF_TYPE_MTD:
259 if (routing == 0) {
260 /* FSPI0 M0 */
261 writel(0x0f0f0000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
262 writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_H);
263 writel(0x00f00000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
264 } else if (routing == 1) {
265 /* FSPI1 M0 */
266 writel(0x0fff0000, PMUIO0_IOC_BASE + GPIO0B_IOMUX_SEL_L);
267 writel(0xff000000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
268 writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_L);
269 } else if (routing == 2) {
270 /* FSPI1 M1 */
271 writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
272 writel(0xf0f00000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
273 }
274 break;
275 default:
276 break;
277 }
278 }
279
280 #ifdef CONFIG_SPL_BUILD
rockchip_stimer_init(void)281 void rockchip_stimer_init(void)
282 {
283 u32 reg;
284
285 /* If Timer already enabled, don't re-init it */
286 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
287 if (reg & 0x1)
288 return;
289 #ifdef COUNTER_FREQUENCY
290 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
291 #endif
292 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
293 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
294 writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04);
295 }
296
spl_board_storages_fixup(struct spl_image_loader * loader)297 void spl_board_storages_fixup(struct spl_image_loader *loader)
298 {
299 if (!loader)
300 return;
301
302 if (loader->boot_device == BOOT_DEVICE_MMC2)
303 /* Unset the sdmmc0 iomux */
304 board_unset_iomux(IF_TYPE_MMC, 1, 0);
305 }
306
tsadc_adjust_bias_current(void)307 static void tsadc_adjust_bias_current(void)
308 {
309 u32 bias, value = 0, width = 0;
310
311 value = readl(SYS_GRF_BASE + TSADC_GRF_ST1);
312 if (!value || value == TSADC_DEF_WIDTH) {
313 printf("Invalid tsadc width\n");
314 } else {
315 width = (value & 0x0000ffff) + ((value & 0xffff0000) >> 16);
316 bias = width * TSADC_DEF_BIAS / TSADC_TARGET_WIDTH;
317 if (bias > TSADC_MAX_BIAS)
318 bias = TSADC_MAX_BIAS;
319 if (bias < TSADC_MIN_BIAS)
320 bias = TSADC_MIN_BIAS;
321 printf("tsadc width=0x%x, bias=0x%x\n", value, bias);
322 writel((TSADC_MAX_BIAS << 16) | bias,
323 SYS_GRF_BASE + TSADC_GRF_CON6);
324 writel(TSADC_UNLOCK_VALUE | TSADC_UNLOCK_VALUE_MASK,
325 SYS_GRF_BASE + TSADC_GRF_CON1);
326 writel(TSADC_UNLOCK_TRIGGER | TSADC_UNLOCK_TRIGGER_MASK,
327 SYS_GRF_BASE + TSADC_GRF_CON1);
328 writel(TSADC_UNLOCK_TRIGGER_MASK, SYS_GRF_BASE + TSADC_GRF_CON1);
329 }
330 }
331
spl_rk_board_prepare_for_jump(struct spl_image_info * spl_image)332 void spl_rk_board_prepare_for_jump(struct spl_image_info *spl_image)
333 {
334 tsadc_adjust_bias_current();
335 }
336
spl_fit_standalone_release(char * id,uintptr_t entry_point)337 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
338 {
339 if (!strcmp(id, "mcu0")) {
340 writel(0x1e001e0, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01);
341 writel(entry_point, SGRF_SYS_BASE + SGRF_HPMCU_BOOT_ADDR);
342 writel(0x1 << 20, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
343 writel(0x1e00000, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01);
344 } else if (!strcmp(id, "mcu1")) {
345 writel(0x1c001c, CRU_PMU_BASE + CRU_PMU_SOFTRST_CON03);
346 writel(entry_point, SGRF_PMU_BASE + SGRF_LPMCU_BOOT_ADDR);
347 writel(0x1 << 23, SGRF_PMU_BASE + SGRF_PMU_SOC_CON0);
348 writel(0x1c0000, CRU_PMU_BASE + CRU_PMU_SOFTRST_CON03);
349 }
350
351 return 0;
352 }
353 #endif
354
355 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)356 int arch_cpu_init(void)
357 {
358 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
359 /* Enable npu pd */
360 writel(0x00010000, PMU2_BASE + PMU2_PWR_GATE_SFTCON0);
361 /* Set emmc master secure */
362 writel(0x10000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
363 /* Set fspi master secure */
364 writel(0x20000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
365 /* Set sdmmc0 master secure */
366 writel(0x40000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
367 /* Set sdmmc1 master secure */
368 writel(0x80000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
369 /* Set rkce master secure */
370 writel(0x80038000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0);
371 /* Set decom master secure */
372 writel(0xC00000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0);
373
374 /* Set all devices slave non-secure */
375 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON0);
376 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON1);
377 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON2);
378 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON3);
379 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON4);
380 writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON5);
381 /* Set OTP to none secure mode */
382 writel(0x00020000, SGRF_SYS_BASE + OTP_SGRF_CON);
383
384 /* Set usb3phy clamp enable */
385 writel(0x40000000, PMU_GRF_BASE + PMU_GRF_SOC_CON0);
386
387 /* Assert the pipe phy reset and de-assert when in use */
388 writel(0x00800080, PERI_CRU_BASE + PERICRU_PERI_SOFTRST_CON01);
389
390 /* Restore pipe phy status to default from phy */
391 writel(0xffff1100, PERI_GRF_BASE + PERI_GRF_USB3DRD_CON1);
392
393 /* Set the USB 2.0 PHY Port1 to enter the sleep mode to save power consumption */
394 writel(0x01ff01d1, PERI_GRF_BASE + PERI_GRF_USB2HOSTPHY_CON0);
395
396 /* Enable tsadc phy */
397 writel(0x01000000, CRU_BUS_BASE + CRU_BUS_GATE_CON06);
398 writel(0x80788028, SYS_GRF_BASE + TSADC_GRF_CON0);
399 writel(0x00ff00a5, SYS_GRF_BASE + TSADC_GRF_CON1);
400 writel(0x01000100, SYS_GRF_BASE + TSADC_GRF_CON1);
401 writel(0x01000000, SYS_GRF_BASE + TSADC_GRF_CON1);
402
403 /* set saradc ibp to 7 */
404 writel(0x00700070, VEPU_GRF_BASE + SARADC0_GRF_CON0);
405 writel(0x00700070, VI_GRF_BASE + SARADC1_GRF_CON0);
406 writel(0x00700070, VI_GRF_BASE + SARADC2_GRF_CON0);
407
408 /* FEPHY: disable gpio's smt and ie, keep high-z to save power consumption */
409 writel(0x00f00000, VCCIO6_IOC_BASE + GPIO6C_PULL);
410 writel(0x00f00000, VCCIO6_IOC_BASE + GPIO6C_IE);
411 writel(0x00f00000, VCCIO6_IOC_BASE + GPIO6C_SMT);
412
413 /* Solve dsm pop pulse */
414 writel(0xfffff990, VCCIO7_IOC_BASE + GRF_DSM_IOC_CON0);
415
416 /* Enable pvtpll for isp/enc/aiisp */
417 writel(0x01ff0064, PVTPLL_ISP_BASE + PVTPLL_GCK_LEN);
418 writel(0x00230023, PVTPLL_ISP_BASE + PVTPLL_GCK_CFG);
419 writel(0x01ff0058, PVTPLL_ENC_BASE + PVTPLL_GCK_LEN);
420 writel(0x00230023, PVTPLL_ENC_BASE + PVTPLL_GCK_CFG);
421 writel(0x01ff0008, PVTPLL_AIISP_BASE + PVTPLL_GCK_LEN);
422 writel(0x00230023, PVTPLL_AIISP_BASE + PVTPLL_GCK_CFG);
423
424 #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
425 board_set_iomux(IF_TYPE_MMC, 0, 0);
426 #elif defined(CONFIG_ROCKCHIP_SFC_IOMUX)
427 /*
428 * (IF_TYPE_MTD, 0, 0) FSPI0
429 * (IF_TYPE_MTD, 1, 0) FSPI1 M0
430 * (IF_TYPE_MTD, 2, 0) FSPI1 M1
431 */
432 board_set_iomux(IF_TYPE_MTD, 0, 0);
433 #endif /* CONFIG_ROCKCHIP_EMMC_IOMUX */
434
435 #if defined(CONFIG_MMC_DW_ROCKCHIP)
436 /* Set the sdmmc iomux and power cycle */
437 board_set_iomux(IF_TYPE_MMC, 1, 0);
438 #endif
439
440 /*
441 * Fix fspi io ds level:
442 *
443 * level 3 for 1V8(default)
444 * level 4 for 3V3
445 */
446 if (readl(VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_H) == 0x1111) {
447 if (readl(VCCIO1_IOC_BASE + GPIO1_IOC_IO1_VSEL) & VCCIO1_VD_3V3) {
448 writel(0x003f001f, VCCIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS_0);
449 writel(0x003f001f, VCCIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS_1);
450 writel(0x3f3f1f1f, VCCIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS_2);
451 writel(0x3f3f1f1f, VCCIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS_3);
452 }
453 }
454 #endif
455
456 return 0;
457 }
458
459 #if defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
460 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_KERNEL_BOOT)
rk_board_fit_image_post_process(void * fit,int node,ulong * load_addr,ulong ** src_addr,size_t * src_len)461 int rk_board_fit_image_post_process(void *fit, int node, ulong *load_addr,
462 ulong **src_addr, size_t *src_len)
463 {
464 struct tag *t;
465 int count;
466
467 /* Only current node is kernel needs go further. */
468 if (!fit_image_check_type(fit, node, IH_TYPE_KERNEL))
469 return 0;
470
471 t = atags_get_tag(ATAG_DDR_MEM);
472 count = t->u.ddr_mem.count;
473 if (!t || !count)
474 return -EINVAL;
475
476 if (t->u.ddr_mem.bank[0] == 0x0) {
477 /*
478 * Change kernel load address for more ddr usable space.
479 * For 32 bits kernel Image: 0x00018000
480 * For 64 bits kernel Image: 0x00200000
481 * For kernel zImage: still 0x45480000
482 */
483 #ifdef CONFIG_CMD_BOOTZ
484 ulong start, end;
485
486 if (bootz_setup((ulong)*src_addr, &start, &end))
487 #endif
488 {
489 uint8_t image_arch;
490
491 if (fit_image_get_arch(fit, node, &image_arch))
492 return -EINVAL;
493
494 if (image_arch == IH_ARCH_ARM) {
495 *load_addr = 0x00018000;
496 } else if (image_arch == IH_ARCH_ARM64) {
497 *load_addr = 0x00200000;
498 } else {
499 printf("Unknown image arch: 0x%x\n", image_arch);
500 return -EINVAL;
501 }
502 printf("Relocate kernel to 0x%lx.\n", *load_addr);
503 }
504 }
505
506 return 0;
507 }
508
board_bidram_fixup(void)509 void board_bidram_fixup(void)
510 {
511 struct memblock *mem;
512 struct tag *t;
513 u64 size = 0;
514 int i, count, n, noffset, num = 0;
515
516 t = atags_get_tag(ATAG_DDR_MEM);
517 count = t->u.ddr_mem.count;
518 if (!t || !count)
519 return;
520 if (t->u.ddr_mem.bank[0] != 0x0)
521 return;
522 size = t->u.ddr_mem.bank[count];
523
524 /* Record current bi_dram banks. */
525 mem = calloc(count + MEM_RESV_COUNT, sizeof(*mem));
526 if (!mem) {
527 printf("Calloc ddr memory failed\n");
528 return;
529 }
530 for (i = 0, n = 0; i < MEM_RESV_COUNT; i++) {
531 if (!gd->bd->bi_dram[i].size)
532 continue;
533 mem[n].base = gd->bd->bi_dram[i].start;
534 mem[n].size = gd->bd->bi_dram[i].size;
535 n++;
536
537 assert(n < MEM_RESV_COUNT);
538 }
539
540 /* Handle that always used as DDR. */
541 gd->bd->bi_dram[num].start = 0x00010000;
542 gd->bd->bi_dram[num].size = 0x0fff0000;
543 num++;
544
545 /* Remap DSMC_MEM to DDR. */
546 noffset = fdt_path_offset(gd->fdt_blob, "/dsmc@21ca0000");
547 if ((noffset >= 0) && fdtdec_get_is_enabled(gd->fdt_blob, noffset)) {
548 #ifdef CONFIG_SPL_BUILD
549 writel(0x08000800, SGRF_PMU_BASE + SGRF_PMU_SOC_CON1);
550 #elif CONFIG_ROCKCHIP_SMCCC
551 sip_smc_secure_reg_write(SGRF_PMU_BASE + SGRF_PMU_SOC_CON1, 0x08000800);
552 #endif
553 gd->bd->bi_dram[num].start = 0x10000000;
554 gd->bd->bi_dram[num].size = 0x10000000;
555 num++;
556 }
557
558 if (size > SZ_512M) {
559 /* Handle that always used as DDR. */
560 gd->bd->bi_dram[num].start = 0x22800000;
561 gd->bd->bi_dram[num].size = 0x01800000;
562 num++;
563
564 /* Remap FSPI_PMU_XIP to DDR. */
565 #ifdef CONFIG_SPL_BUILD
566 writel(0x20002000, SGRF_PMU_BASE + SGRF_PMU_SOC_CON1);
567 #elif CONFIG_ROCKCHIP_SMCCC
568 sip_smc_secure_reg_write(SGRF_PMU_BASE + SGRF_PMU_SOC_CON1, 0x20002000);
569 #endif
570 gd->bd->bi_dram[num].start = 0x24000000;
571 gd->bd->bi_dram[num].size = 0x02000000;
572 num++;
573
574 /* Handle that always used as DDR. */
575 gd->bd->bi_dram[num].start = 0x26000000;
576 gd->bd->bi_dram[num].size = 0x02000000;
577 num++;
578
579 /* Remap FSPI_XIP to DDR. */
580 #ifdef CONFIG_SPL_BUILD
581 writel(0x10001000, SGRF_PMU_BASE + SGRF_PMU_SOC_CON1);
582 #elif CONFIG_ROCKCHIP_SMCCC
583 sip_smc_secure_reg_write(SGRF_PMU_BASE + SGRF_PMU_SOC_CON1, 0x10001000);
584 #endif
585 gd->bd->bi_dram[num].start = 0x28000000;
586 gd->bd->bi_dram[num].size = 0x08000000;
587 num++;
588
589 /* Handle that always used as DDR. */
590 gd->bd->bi_dram[num].start = 0x30000000;
591 gd->bd->bi_dram[num].size = 0x0ff1e000;
592 num++;
593 }
594
595 /* Append recorded bi_dram banks. */
596 for (n = 0; n < MEM_RESV_COUNT; n++) {
597 if (!mem[n].size)
598 continue;
599 gd->bd->bi_dram[num].start = mem[n].base;
600 gd->bd->bi_dram[num].size = mem[n].size;
601 num++;
602
603 assert(num < MEM_RESV_COUNT);
604 }
605 }
606
spl_fdt_fixup_memory(struct spl_image_info * spl_image)607 void spl_fdt_fixup_memory(struct spl_image_info *spl_image)
608 {
609 struct memblock *list;
610 void *blob = spl_image->fdt_addr;
611 u64 start[CONFIG_NR_DRAM_BANKS];
612 u64 size[CONFIG_NR_DRAM_BANKS];
613 int i, count = 0;
614
615 if (fdt_check_header(blob)) {
616 printf("Invalid dtb\n");
617 return;
618 }
619
620 list = param_parse_ddr_mem(&count);
621 if (!list) {
622 printf("Can't get dram banks\n");
623 return;
624 }
625
626 if (count > CONFIG_NR_DRAM_BANKS) {
627 printf("Dram banks num=%d, over %d\n", count, CONFIG_NR_DRAM_BANKS);
628 return;
629 }
630
631 for (i = 0; i < count; i++) {
632 gd->bd->bi_dram[i].start = list[i].base < SZ_1G ? SZ_1G : list[i].base;
633 gd->bd->bi_dram[i].size = ddr_mem_get_usable_size(list[i].base, list[i].size);
634 }
635
636 board_bidram_fixup();
637
638 for (i = 0, count = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
639 start[i] = gd->bd->bi_dram[i].start;
640 size[i] = gd->bd->bi_dram[i].size;
641 if (size[i] == 0)
642 continue;
643 debug("Adding bank: 0x%08llx - 0x%08llx (size: 0x%08llx)\n",
644 start[i], start[i] + size[i], size[i]);
645 count++;
646 }
647
648 fdt_increase_size(blob, 512);
649
650 if (fdt_fixup_memory_banks(blob, start, size, count)) {
651 printf("Fixup kernel dtb memory node failed.\n");
652 return;
653 }
654
655 return;
656 }
657
board_bidram_append_size(void)658 u64 board_bidram_append_size(void)
659 {
660 struct tag *t;
661 int count;
662
663 t = atags_get_tag(ATAG_DDR_MEM);
664 count = t->u.ddr_mem.count;
665 if (!t || !count)
666 return 0;
667
668 if (t->u.ddr_mem.bank[0] == 0x0)
669 return t->u.ddr_mem.bank[count] > SZ_1G ?
670 SZ_1G : t->u.ddr_mem.bank[count];
671
672 return 0;
673 }
674
675 #endif
676 #endif
677 #endif
678
fit_standalone_release(char * id,uintptr_t entry_point)679 int fit_standalone_release(char *id, uintptr_t entry_point)
680 {
681 if (!strcmp(id, "hpmcu")) {
682 writel(0x1e001e0, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01);
683 sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
684 ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
685 entry_point);
686 writel(0x1e00000, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01);
687 }
688
689 return 0;
690 }
691
692 #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) && defined(CONFIG_ROCKCHIP_SFC_IOMUX)
693 #error FSPI0 M0 and eMMC iomux is incompatible for rv1126b Soc. You should disable one of them.
694 #endif
695