Searched refs:PORT_LOGIC_LINK_WIDTH_4_LANES (Results 1 – 2 of 2) sorted by relevance
70 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) macro292 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; in pcie_link_set_lanes()
137 #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) macro426 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; in rk_pcie_configure()