| /rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock-k2hk.h | 39 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
40 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
41 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
42 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3368-dmc.txt | 8 (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
19 the DDR3 device's speed-bin (as specified according to JESD-79)
51 Example (for DDR3-1600K and 800MHz)
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| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | Kconfig | 80 Enable Freescale DDR3 controller for PowerPC SoCs.
86 Enable Freescale DDR3 controller for ARM SoCs.
118 bool "Freescale DDR3 controller"
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| /rk3399_rockchip-uboot/board/toradex/colibri_imx6/ |
| H A D | 800mhz_2x64mx16.cfg | 18 /* DDR3 DATA BUS SIZE: 64BIT */
20 /* DDR3 DATA BUS SIZE: 32BIT */
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| H A D | 800mhz_4x64mx16.cfg | 18 /* DDR3 DATA BUS SIZE: 64BIT */
20 /* DDR3 DATA BUS SIZE: 32BIT */
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| /rk3399_rockchip-uboot/board/gdsys/a38x/ |
| H A D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/CZ.NIC/turris_omnia/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | Kconfig | 242 bool "DDR3 1333"
272 Set the dram type, 3: DDR3, 7: LPDDR3
285 (for DDR3-1600) are 312 to 792.
355 Select the timings of the DDR3 chips.
363 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
365 Use the timings of the standard JEDEC DDR3-1066F speed bin for
366 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
367 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
368 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
369 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
[all …]
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| /rk3399_rockchip-uboot/board/Marvell/db-mv784mp-gp/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/Synology/ds414/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/Marvell/db-88f6720/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/solidrun/clearfog/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/Marvell/db-88f6820-gp/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/maxbcm/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/theadorable/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/Marvell/db-88f6820-amc/ |
| H A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /rk3399_rockchip-uboot/board/seco/mx6quq7/ |
| H A D | mx6quq7-2g.cfg | 77 * DDR3 SETTINGS
116 * in DDR3, 64-bit mode, only MMDC0 is init
136 /* Initialize DDR3 on CS_0 and CS_1 */
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| /rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/ |
| H A D | README | 13 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
17 * DDR3
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 13 DDR3 = 3, enumerator
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1108/ |
| H A D | Kconfig | 13 * 128M DDR3
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rv1126.c | 799 else if (dramtype == DDR3) in get_ddr_drv_odt_info()
966 if (dramtype == DDR3) { in set_ds_odt()
1023 if (dramtype != DDR3 && dram_odt_ohm) in set_ds_odt()
1092 if (dramtype == DDR3 || dramtype == DDR4) { in set_ds_odt()
1102 if (dramtype == DDR3) { in set_ds_odt()
1207 if (dramtype == DDR4 || dramtype == DDR3) { in set_ds_odt()
1659 if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2) in data_training_wl()
1662 if (dramtype == DDR3 || dramtype == DDR4) in data_training_wl()
1693 if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2) in data_training_wl()
1726 if (dramtype == DDR3 && vref_inner == 0x80) { in data_training_rd()
[all …]
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| H A D | sdram_rv1108_pctl_phy.c | 116 if (params_priv->ddr_config_t.ddr_type == DDR3 || in memory_init()
139 if (params_priv->ddr_config_t.ddr_type == DDR3) { in memory_init()
294 if (params_priv->ddr_config_t.ddr_type == DDR3 || in pctl_cfg()
305 if (params_priv->ddr_config_t.ddr_type == DDR3) in pctl_cfg()
384 case DDR3: in phy_cfg()
480 if (params_priv->ddr_config_t.ddr_type == DDR3) { in sdram_detect()
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| H A D | Kconfig | 32 3 for DDR3, 5 for LPDDR2, 6 for LPDDR3, 7 for LPDDR4, all other
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| H A D | sdram-px30-ddr3-detect-333.inc | 28 .dramtype = DDR3,
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rv1126/ |
| H A D | sdram-rv1126-ddr3-detect-664.inc | 28 .dramtype = DDR3,
|