Home
last modified time | relevance | path

Searched refs:smmu_base (Results 1 – 9 of 9) sorted by relevance

/rk3399_ARM-atf/drivers/arm/smmu/
H A Dsmmu_v3.c41 int __init smmuv3_security_init(uintptr_t smmu_base) in smmuv3_security_init() argument
44 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) in smmuv3_security_init()
51 mmio_setbits_32(smmu_base + SMMU_GBPA, in smmuv3_security_init()
54 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) in smmuv3_security_init()
58 if ((mmio_read_32(smmu_base + SMMU_S_IDR1) & in smmuv3_security_init()
63 if (smmuv3_poll(smmu_base + SMMU_S_GBPA, SMMU_S_GBPA_UPDATE, 0U) != 0U) in smmuv3_security_init()
66 mmio_setbits_32(smmu_base + SMMU_S_GBPA, in smmuv3_security_init()
69 return smmuv3_poll(smmu_base + SMMU_S_GBPA, SMMU_S_GBPA_UPDATE, 0U); in smmuv3_security_init()
73 int __init smmuv3_init(uintptr_t smmu_base) in smmuv3_init() argument
90 mmio_write_32(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL); in smmuv3_init()
[all …]
/rk3399_ARM-atf/include/drivers/arm/
H A Dsmmu_v3.h68 int smmuv3_init(uintptr_t smmu_base);
69 int smmuv3_security_init(uintptr_t smmu_base);
71 int smmuv3_ns_set_abort_all(uintptr_t smmu_base);
/rk3399_ARM-atf/plat/qti/msm8916/
H A Dmsm8916_config.c138 static void msm8916_smmu_cache_unlock(uintptr_t smmu_base, uintptr_t clk_cbcr) in msm8916_smmu_cache_unlock() argument
146 version = mmio_read_32(smmu_base + SMMU_IDR7); in msm8916_smmu_cache_unlock()
147 VERBOSE("SMMU(0x%lx) r%dp%d\n", smmu_base, in msm8916_smmu_cache_unlock()
152 mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK); in msm8916_smmu_cache_unlock()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dbl31_setup.c394 uintptr_t smmu_base = SMMU_BASE; in brcm_stingray_smmu_init() local
400 val = mmio_read_32(smmu_base + 0x0); in brcm_stingray_smmu_init()
402 mmio_write_32(smmu_base + 0x0, val); in brcm_stingray_smmu_init()
409 mmio_read_32(smmu_base + 0x0), in brcm_stingray_smmu_init()
410 mmio_read_32(smmu_base + 0x4), in brcm_stingray_smmu_init()
411 mmio_read_32(smmu_base + 0x8)); in brcm_stingray_smmu_init()
414 mmio_read_32(smmu_base + 0x20), in brcm_stingray_smmu_init()
415 mmio_read_32(smmu_base + 0x24), in brcm_stingray_smmu_init()
416 mmio_read_32(smmu_base + 0x28)); in brcm_stingray_smmu_init()
419 mmio_read_32(smmu_base + 0x2c), in brcm_stingray_smmu_init()
[all …]
H A Diommu.c291 uintptr_t smmu_base = SMMU_BASE; in arm_smmu_enable_secure_client_port() local
293 mmio_clrbits_32(smmu_base, sCR0_CLIENTPD); in arm_smmu_enable_secure_client_port()
298 uintptr_t smmu_base = SMMU_BASE; in arm_smmu_reserve_secure_cntxt() local
300 mmio_clrsetbits_32(smmu_base + ARM_SMMU_SMMU_SCR1, in arm_smmu_reserve_secure_cntxt()
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl31_plat_setup.c31 static void configure_smmu_cache_unlock(uintptr_t smmu_base);
67 static void configure_smmu_cache_unlock(uintptr_t smmu_base) in configure_smmu_cache_unlock() argument
71 version = mmio_read_32(smmu_base + SMMU_IDR7); in configure_smmu_cache_unlock()
72 VERBOSE("SOCFPGA: SMMU(0x%lx) r%dp%d\n", smmu_base, in configure_smmu_cache_unlock()
77 mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK); in configure_smmu_cache_unlock()
/rk3399_ARM-atf/include/services/
H A Drmm_core_manifest.h112 uint64_t smmu_base; /* SMMUv3 base address */ member
116 CASSERT(offsetof(struct smmu_info, smmu_base) == 0UL,
/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_common.c962 smmu_ptr[0].smmu_base = FVP_RMM_SMMU_BASE; in plat_rmmd_load_manifest()
/rk3399_ARM-atf/docs/components/
H A Drmm-el3-comms-spec.rst1232 | smmu_base | 0 | uint64_t | SMMU Base address |