11154586bSJeenu Viswambharan /* 2*90552c61SAlexeiFedorov * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved. 31154586bSJeenu Viswambharan * 41154586bSJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 51154586bSJeenu Viswambharan */ 61154586bSJeenu Viswambharan 7c3cf06f1SAntonio Nino Diaz #ifndef SMMU_V3_H 8c3cf06f1SAntonio Nino Diaz #define SMMU_V3_H 91154586bSJeenu Viswambharan 101154586bSJeenu Viswambharan #include <stdint.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1252a314afSOlivier Deprez #include <platform_def.h> 131154586bSJeenu Viswambharan 141154586bSJeenu Viswambharan /* SMMUv3 register offsets from device base */ 156c5c5320SLucian Paul-Trifu #define SMMU_CR0 U(0x0020) 166c5c5320SLucian Paul-Trifu #define SMMU_CR0ACK U(0x0024) 17ccd4d475SAlexei Fedorov #define SMMU_GBPA U(0x0044) 186d5f0631SAntonio Nino Diaz #define SMMU_S_IDR1 U(0x8004) 196d5f0631SAntonio Nino Diaz #define SMMU_S_INIT U(0x803c) 20ccd4d475SAlexei Fedorov #define SMMU_S_GBPA U(0x8044) 21ccd4d475SAlexei Fedorov 2252a314afSOlivier Deprez /* 2352a314afSOlivier Deprez * TODO: SMMU_ROOT_PAGE_OFFSET is platform specific. 2452a314afSOlivier Deprez * Currently defined as a command line model parameter. 2552a314afSOlivier Deprez */ 2652a314afSOlivier Deprez #if ENABLE_RME 2752a314afSOlivier Deprez 2852a314afSOlivier Deprez #define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET) 2952a314afSOlivier Deprez #define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000) 3052a314afSOlivier Deprez #define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008) 3152a314afSOlivier Deprez #define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020) 3252a314afSOlivier Deprez #define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024) 3352a314afSOlivier Deprez #define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028) 3452a314afSOlivier Deprez #define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030) 3552a314afSOlivier Deprez #define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038) 3652a314afSOlivier Deprez #define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040) 3752a314afSOlivier Deprez #define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050) 3852a314afSOlivier Deprez #define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058) 3952a314afSOlivier Deprez 4052a314afSOlivier Deprez #endif /* ENABLE_RME */ 4152a314afSOlivier Deprez 426c5c5320SLucian Paul-Trifu /* SMMU_CR0 and SMMU_CR0ACK register fields */ 436c5c5320SLucian Paul-Trifu #define SMMU_CR0_SMMUEN (1UL << 0) 446c5c5320SLucian Paul-Trifu 45ccd4d475SAlexei Fedorov /* SMMU_GBPA register fields */ 46ccd4d475SAlexei Fedorov #define SMMU_GBPA_UPDATE (1UL << 31) 47ccd4d475SAlexei Fedorov #define SMMU_GBPA_ABORT (1UL << 20) 481154586bSJeenu Viswambharan 491154586bSJeenu Viswambharan /* SMMU_S_IDR1 register fields */ 50ccd4d475SAlexei Fedorov #define SMMU_S_IDR1_SECURE_IMPL (1UL << 31) 511154586bSJeenu Viswambharan 521154586bSJeenu Viswambharan /* SMMU_S_INIT register fields */ 53ccd4d475SAlexei Fedorov #define SMMU_S_INIT_INV_ALL (1UL << 0) 541154586bSJeenu Viswambharan 55ccd4d475SAlexei Fedorov /* SMMU_S_GBPA register fields */ 56ccd4d475SAlexei Fedorov #define SMMU_S_GBPA_UPDATE (1UL << 31) 57ccd4d475SAlexei Fedorov #define SMMU_S_GBPA_ABORT (1UL << 20) 581154586bSJeenu Viswambharan 5952a314afSOlivier Deprez /* SMMU_ROOT_IDR0 register fields */ 6052a314afSOlivier Deprez #define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0) 61*90552c61SAlexeiFedorov #define SMMU_ROOT_IDR0_BA_REALM_SHIFT 22U 62*90552c61SAlexeiFedorov #define SMMU_ROOT_IDR0_BA_REALM_MASK GENMASK_32(31U, SMMU_ROOT_IDR0_BA_REALM_SHIFT) 6352a314afSOlivier Deprez 6452a314afSOlivier Deprez /* SMMU_ROOT_CR0 register fields */ 6552a314afSOlivier Deprez #define SMMU_ROOT_CR0_GPCEN (1UL << 1) 6652a314afSOlivier Deprez #define SMMU_ROOT_CR0_ACCESSEN (1UL << 0) 6752a314afSOlivier Deprez 681154586bSJeenu Viswambharan int smmuv3_init(uintptr_t smmu_base); 691461ad9fSAlexei Fedorov int smmuv3_security_init(uintptr_t smmu_base); 701154586bSJeenu Viswambharan 716c5c5320SLucian Paul-Trifu int smmuv3_ns_set_abort_all(uintptr_t smmu_base); 726c5c5320SLucian Paul-Trifu 73c3cf06f1SAntonio Nino Diaz #endif /* SMMU_V3_H */ 74