| /rk3399_ARM-atf/drivers/brcm/ |
| H A D | sotp.c | 262 int row; in sotp_read_key() local
269 row = start_row; in sotp_read_key()
270 while ((keysize > 0) && (row <= end_row)) { in sotp_read_key()
271 row_data = sotp_mem_read(row, SOTP_ROW_ECC); in sotp_read_key()
279 row++; in sotp_read_key()
282 if ((status2 == 0xFFFFFFFF) || (status == 0) || (row > end_row)) in sotp_read_key()
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| /rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/ |
| H A D | boot_init_dram_regdef.h | 24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
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| /rk3399_ARM-atf/drivers/qti/accesscontrol/vmidmt/ |
| H A D | vmidmt.c | 247 const struct vmidmt_err_pos_to_hal_map *row = in log_errors() local
250 for (size_t i = 0; i < ACC_VMIDMT_ERR_NUM_PER_REG; i++, row++) { in log_errors()
251 if (row->bit_pos != pos) in log_errors()
254 if (row->vmidmt != HAL_VMIDMT_COUNT) in log_errors()
255 log_error(row->vmidmt); in log_errors()
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_memory_controller.c | 176 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
191 row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
195 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /rk3399_ARM-atf/plat/intel/soc/agilex/soc/ |
| H A D | agilex_memory_controller.c | 175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
190 row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
194 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_memory_controller.c | 204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
219 row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
223 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /rk3399_ARM-atf/drivers/qti/accesscontrol/xpu/ |
| H A D | xpu3.c | 171 struct xpu_err_pos_to_hal_map *row; in xpu_print_log() local
177 row = xpu_err_pos_to_hal_map[reg]; in xpu_print_log()
179 for (size_t i = 0; row[i].bit_mask != 0; i++) { in xpu_print_log()
185 m = &row[i]; in xpu_print_log()
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| /rk3399_ARM-atf/tools/memory/src/memory/ |
| H A D | summary.py | 466 row = [i]
469 row.append(
475 table.add_row(row)
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| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi | 15 * Addressing RBC row/bank interleaving
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| H A D | stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi | 15 * Addressing RBC row/bank interleaving
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| H A D | stm32mp25-lpddr4-2x16Gbits-32bits-1200MHz.dtsi | 15 * Addressing RBC row/bank interleaving
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| H A D | stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi | 17 * Addressing RBC row/bank interleaving
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| H A D | stm32mp25-ddr4-2x16Gbits-2x16bits-1200MHz.dtsi | 17 * Addressing RBC row/bank interleaving
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| H A D | stm32mp21-lpddr4-1x16Gbits-1x16bits-800MHz.dtsi | 15 * Addressing RBC row/bank interleaving
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| H A D | stm32mp23-lpddr4-1x16Gbits-1x16bits-1200MHz.dtsi | 15 * Addressing RBC row/bank interleaving
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| /rk3399_ARM-atf/include/plat/marvell/odyssey/csr/ |
| H A D | ody-csrs-mdc.h | 343 uint64_t row : 14; member
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | dfs.c | 89 uint32_t row; in get_cs_die_capability() local
91 row = cs == 0 ? ch->cs0_row : ch->cs1_row; in get_cs_die_capability()
95 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + in get_cs_die_capability()
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