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Searched refs:pwr_req (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/
H A Dgpc.c81 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
84 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
132 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
135 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
/rk3399_ARM-atf/plat/imx/imx8m/include/
H A Dgpc.h33 .pwr_req = name##_PWR_REQ, \
41 .pwr_req = name##_PWR_REQ, \
50 uint32_t pwr_req; member
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm.c782 unsigned int pwr_req = req->req; in cpupm_invoke() local
814 if (pwr_req & MT_CPUPM_PWR_DOMAIN_CLUSTER) in cpupm_invoke()
815 pwr_req |= in cpupm_invoke()
818 pwr_req = pwr_req & ~req->stat.sta_req; in cpupm_invoke()
820 if (pwr_req & MT_CPUPM_PWR_DOMAIN_CLUSTER) in cpupm_invoke()
823 if ((pwr_req & MT_CPUPM_MCUSYS_REQ) && in cpupm_invoke()
827 req->stat.sta_req |= pwr_req; in cpupm_invoke()
829 if (pwr_req & MT_CPUPM_PWR_DOMAIN_CLUSTER) in cpupm_invoke()
830 pwr_req |= in cpupm_invoke()
833 pwr_req = pwr_req & req->stat.sta_req; in cpupm_invoke()
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/
H A Dgpc.c143 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
146 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
299 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
302 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/
H A Dgpc.c208 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
211 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()
272 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
275 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()