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/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
79 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) argument
80 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) argument
81 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) argument
82 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) argument
84 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) argument
85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) argument
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.h13 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) argument
14 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) argument
15 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) argument
16 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ argument
17 (n < 8 ? SGRF_SOC_CON3_7(n) :\
18 SGRF_SOC_CON8_15(n)))
20 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) argument
21 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) argument
22 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) argument
23 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) argument
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h44 #define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4)) argument
67 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) argument
69 #define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4) argument
70 #define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4) argument
71 #define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * 4) argument
73 #define GRF_SOC_CON(n) (0x400 + (n) * 4) argument
74 #define GRF_SOC_STATUS(n) (0x480 + (n) * 4) argument
75 #define GRF_CPU_STATUS(n) (0x520 + (n) * 4) argument
76 #define GRF_OS_REG(n) (0x5c8 + (n) * 4) argument
77 #define DDRGRF_SOC_CON(n) (0x000 + (n) * 4) argument
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.h15 #define PMUCRU_PPLL_CON(n) ((n) * 4) argument
16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
29 #define FBDIV(n) ((0xfff << 16) | n) argument
30 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) argument
31 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) argument
32 #define REFDIV(n) ((0x3F << 16) | n) argument
33 #define PLL_LOCK(n) ((n >> 31) & 0x1) argument
46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) argument
56 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) argument
57 #define CRU_GATE_CON(n) (0x300 + (n) * 4) argument
[all …]
/rk3399_ARM-atf/plat/allwinner/common/include/
H A Dsunxi_cpucfg_ncat.h20 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
21 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
23 #define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4) argument
25 #define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4) argument
26 #define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x40 + (n) * 8) argument
27 #define SUNXI_ALT_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x44 + (n) * 8) argument
31 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
32 (c) * 0x10 + (n) * 4)
33 #define SUNXI_CPU_UNK_REG(n) (SUNXI_R_CPUCFG_BASE + 0x0070 + (n) * 4) argument
/rk3399_ARM-atf/drivers/arm/gic/common/
H A Dgic_common.c25 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
27 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
36 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
38 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); in gicd_read_isenabler()
47 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
49 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); in gicd_read_icenabler()
58 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
60 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
69 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
71 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); in gicd_read_icpendr()
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar_gen4/mssr/
H A Dmssr.c15 #define MSSR_SRCR(n) (MSSR_BASE + 0x2C00U + (n) * 4) argument
16 #define MSSR_SRSTCLR(n) (MSSR_BASE + 0x2C80U + (n) * 4) argument
17 #define MSSR_MSTPCR(n) (MSSR_BASE + 0x2D00U + (n) * 4) argument
18 #define MSSR_MSTPSR(n) (MSSR_BASE + 0x2E00U + (n) * 4) argument
26 void rcar_mssr_clock(unsigned int n, uint32_t data, bool on, bool force) in rcar_mssr_clock() argument
30 prev_status = mmio_read_32(MSSR_MSTPSR(n)); in rcar_mssr_clock()
40 cpg_write_32(MSSR_MSTPCR(n), next_status); in rcar_mssr_clock()
43 while ((data & mmio_read_32(MSSR_MSTPSR(n))) != 0) in rcar_mssr_clock()
46 while ((data & mmio_read_32(MSSR_MSTPSR(n))) == 0) in rcar_mssr_clock()
50 void rcar_mssr_soft_reset(unsigned int n, uint32_t data, bool assert, bool force) in rcar_mssr_soft_reset() argument
[all …]
/rk3399_ARM-atf/lib/compiler-rt/builtins/
H A Dudivmoddi4.c30 udwords n; in __udivmoddi4() local
31 n.all = a; in __udivmoddi4()
38 if (n.s.high == 0) { in __udivmoddi4()
44 *rem = n.s.low % d.s.low; in __udivmoddi4()
45 return n.s.low / d.s.low; in __udivmoddi4()
51 *rem = n.s.low; in __udivmoddi4()
61 *rem = n.s.high % d.s.low; in __udivmoddi4()
62 return n.s.high / d.s.low; in __udivmoddi4()
65 if (n.s.low == 0) { in __udivmoddi4()
70 r.s.high = n.s.high % d.s.high; in __udivmoddi4()
[all …]
H A Dint_div_impl.inc16 static __inline fixuint_t __udivXi3(fixuint_t n, fixuint_t d) {
19 unsigned sr = (d ? clz(d) : N) - (n ? clz(n) : N);
21 if (sr > N - 1) // n < d
24 return n;
27 fixuint_t r = n >> sr;
28 n <<= N - sr;
31 r = (r << 1) | (n >> (N - 1));
32 n = (n << 1) | carry;
40 n = (n << 1) | carry;
41 return n;
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicdv2_helpers.c24 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
26 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
35 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
37 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); in gicd_read_isenabler()
46 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
48 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); in gicd_read_icenabler()
57 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
59 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); in gicd_read_ispendr()
68 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
70 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); in gicd_read_icpendr()
[all …]
/rk3399_ARM-atf/lib/libc/
H A Dsnprintf.c32 static void string_print(char **s, size_t n, size_t *chars_printed, in string_print() argument
36 CHECK_AND_PUT_CHAR(*s, n, *chars_printed, *str); in string_print()
41 static void unsigned_num_print(char **s, size_t n, size_t *chars_printed, in unsigned_num_print() argument
72 CHECK_AND_PUT_CHAR(*s, n, *chars_printed, padc); in unsigned_num_print()
75 CHECK_AND_PUT_CHAR(*s, n, *chars_printed, num_buf[i - 1]); in unsigned_num_print()
78 CHECK_AND_PUT_CHAR(*s, n, *chars_printed, padc); in unsigned_num_print()
109 int vsnprintf(char *s, size_t n, const char *fmt, va_list args) in vsnprintf() argument
121 if (n == 0U) { in vsnprintf()
123 } else if (n == 1U) { in vsnprintf()
126 n = 0U; in vsnprintf()
[all …]
H A Dqsort.c67 #define vecswap(a, b, n) \ argument
68 if ((n) > 0) swapfunc(a, b, n)
104 local_qsort(void *a, size_t n, size_t es, cmp_t *cmp, void *thunk) in local_qsort() argument
112 if (__predict_false(n < 2)) in local_qsort()
116 if (n < 7) { in local_qsort()
117 for (pm = (char *)a + es; pm < (char *)a + n * es; pm += es) in local_qsort()
124 pm = (char *)a + (n / 2) * es; in local_qsort()
125 if (n > 7) { in local_qsort()
127 pn = (char *)a + (n - 1) * es; in local_qsort()
128 if (n > 40) { in local_qsort()
[all …]
/rk3399_ARM-atf/docs/resources/diagrams/plantuml/
H A Drse_attestation_flow.puml17 RMM -> BL31: get_realm_key(\n\t**hash_algo**, ...)
20 Rnote over DelegAttest: Compute input\n\ for key derivation\n\ (hash of measurements)
22 Rnote over DelegAttest: Compute public key\n\ hash with **hash_algo**.
23 Rnote over Crypto: Seed is provisioned\n\ in the factory.
26 Rnote over RMM: Only private key\n\ is returned. Public\n\ key and its hash\n\ must be computed.\n\
27 Public key is included\n\ in the realm token.\n\ Its hash is the input\n\ for get_platform_token
28 RMM -> BL31: get_platform_token(\n\t**pub_key_hash**, ...)
30 Rnote over DelegAttest: Check **pub_key_hash**\n\ against derived key.
32 Rnote over InitAttest: Create the token including\n\ the **pub_key_hash** as the\n\ challenge claim
38 Rnote over RMM: Platform token is\n\ cached. It is not\n\ changing within\n\ a power cycle.
/rk3399_ARM-atf/include/drivers/rpi3/gpio/
H A Drpi3_gpio.h18 #define RPI3_GPIO_GPFSEL(n) ((n) * U(0x04)) argument
19 #define RPI3_GPIO_GPSET(n) (((n) * U(0x04)) + U(0x1C)) argument
20 #define RPI3_GPIO_GPCLR(n) (((n) * U(0x04)) + U(0x28)) argument
21 #define RPI3_GPIO_GPLEV(n) (((n) * U(0x04)) + U(0x34)) argument
23 #define RPI3_GPIO_GPPUDCLK(n) (((n) * U(0x04)) + U(0x98)) argument
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.h15 #define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n)) argument
30 #define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4) argument
31 #define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4) argument
32 #define SGRF_CPU_CON(n) (0x40 + (n) * 4) argument
33 #define SGRF_SOC_STATUS(n) (0x100 + (n) * 4) argument
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/ddr/
H A Dddr_rk3368.h206 #define SET_NR(n) ((0x3f << (8 + 16)) | ((n - 1) << 8)) argument
207 #define SET_NO(n) ((0xf << (0 + 16)) | ((n - 1) << 0)) argument
208 #define SET_NF(n) ((n - 1) & 0x1fff) argument
209 #define SET_NB(n) ((n - 1) & 0xfff) argument
210 #define PLLMODE(n) ((0x3 << (8 + 16)) | (n << 8)) argument
218 #define DDRMSCH0_SRSTN_REQ(n) (((0x1 << 10) << 16) | (n << 10)) argument
219 #define DDRCTRL0_PSRSTN_REQ(n) (((0x1 << 3) << 16) | (n << 3)) argument
220 #define DDRCTRL0_SRSTN_REQ(n) (((0x1 << 2) << 16) | (n << 2)) argument
221 #define DDRPHY0_PSRSTN_REQ(n) (((0x1 << 1) << 16) | (n << 1)) argument
222 #define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0)) argument
/rk3399_ARM-atf/lib/debugfs/
H A Ddevfip.c98 int n; in get_entry() local
100 n = devtab[c->index]->read(c, entry, sizeof(struct fip_entry)); in get_entry()
101 if (n <= 0) { in get_entry()
102 return n; in get_entry()
105 if (n != sizeof(struct fip_entry)) { in get_entry()
119 static int fipgen(chan_t *c, const dirtab_t *tab, int ntab, int n, dir_t *dir) in fipgen() argument
139 for (i = 0; i <= n; i++) { in fipgen()
165 entry.size, n, O_READ); in fipgen()
168 make_dir_entry(c, dir, unk, entry.size, n, O_READ); in fipgen()
188 static int fipread(chan_t *c, void *buf, int n) in fipread() argument
[all …]
/rk3399_ARM-atf/fdts/
H A Dfvp-defs-dynamiq.dtsi27 * n - CPU number
30 #define CPU(n, r) \ argument
31 CPU##n:cpu@r## { \
41 #define THREAD(n) \ argument
42 thread##n { \
46 #define CORE(n) \ argument
47 core##n { \
53 #define CORE(n) \ argument
54 core##n { \
55 cpu = <&CPU##n>;\
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dplat_conf.mk26 MT_SPMFW_LOAD_BY_DRAM_TYPE := n
29 MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT := n
33 MT_SPM_UART_SUSPEND_SUPPORT := n
36 MT_SPM_PMIC_WRAP_DUMP_SUPPORT := n
39 MT_SPM_TIMESTAMP_SUPPORT := n
46 ifeq (${MT_SPM_FEATURE_SUPPORT},n)
52 ifeq (${MT_SPMFW_LOAD_BY_DRAM_TYPE},n)
56 ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT},n)
60 ifeq (${MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT},n)
68 ifeq (${MT_SPM_UART_SUSPEND_SUPPORT},n)
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/dmc/
H A Ddmc_rk3576.h13 #define GRF_CH_CON(ch, n) ((((ch) % 2) * 0x100) + ((n) * 4)) argument
15 #define GRF_DDRPHY_CON(n) (0x530 + ((n) * 4)) argument
17 #define DDR_GRF_COMMON_CON(n) (0x540 + ((n) * 4)) argument
20 #define PMUGRF_OS_REG(n) (0x200 + ((n) * 4)) argument
/rk3399_ARM-atf/drivers/allwinner/
H A Dsunxi_msgbox.c22 #define RX_IRQ(n) BIT(0 + 2 * (n)) argument
23 #define TX_IRQ(n) BIT(1 + 2 * (n)) argument
25 #define FIFO_STAT_REG(n) (0x0100 + 0x4 * (n)) argument
28 #define MSG_STAT_REG(n) (0x0140 + 0x4 * (n)) argument
31 #define MSG_DATA_REG(n) (0x0180 + 0x4 * (n)) argument
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600ae_fmu_helpers.c31 #define GIC_FMU_WRITE_64(base, reg, n, val) \ argument
42 mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
43 mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
76 #define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \ argument
81 GIC_FMU_WRITE_64(base, reg, n, val); \
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n) in gic_fmu_read_errfr() argument
100 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U); in gic_fmu_read_errfr()
102 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32); in gic_fmu_read_errfr()
110 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n) in gic_fmu_read_errctlr() argument
116 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U); in gic_fmu_read_errctlr()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dplat_conf.mk20 MT_SPMFW_LOAD_BY_DRAM_TYPE := n
23 MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT := n
27 MT_SPM_UART_SUSPEND_SUPPORT := n
30 MT_SPM_PMIC_WRAP_DUMP_SUPPORT := n
33 MT_SPM_TIMESTAMP_SUPPORT := n
39 MT_SPM_COMMON_SODI_SUPPORT := n
57 ifeq (${MT_SPM_FEATURE_SUPPORT},n)
63 ifeq (${MT_SPMFW_LOAD_BY_DRAM_TYPE},n)
67 ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT},n)
71 ifeq (${MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT},n)
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.h89 #define PMU1GRF_SOC_CON(n) ((n) * 4) argument
91 #define PMU1GRF_OS_REG(n) (0x200 + ((n) * 4)) argument
100 #define SYS_GRF_NOC_CON(n) (0x100 + (n) * 4) argument
101 #define SYS_GRF_SOC_CON(n) (0x300 + (n) * 4) argument
102 #define SYS_GRF_SOC_STATUS(n) (0x380 + (n) * 4) argument
140 #define STIMER0_CHN_BASE(n) (STIMER0_BASE + 0x20 * (n)) argument
141 #define STIMER1_CHN_BASE(n) (STIMER1_BASE + 0x20 * (n)) argument
/rk3399_ARM-atf/include/plat/arm/css/common/
H A Dcss_pm.h57 #define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ argument
59 #define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
60 #define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ argument
62 #define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument

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