| /rk3399_ARM-atf/drivers/arm/gic/v3/ |
| H A D | gicv3_main.c | 106 assert(plat_driver_data->gicd_base != 0U); in gicv3_driver_init()
124 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); in gicv3_driver_init()
136 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); in gicv3_driver_init()
175 gicv3_check_erratas_applies(plat_driver_data->gicd_base); in gicv3_driver_init()
191 assert(gicv3_driver_data->gicd_base != 0U); in gicv3_distif_init()
200 gicd_clr_ctlr(gicv3_driver_data->gicd_base, in gicv3_distif_init()
207 gicd_set_ctlr(gicv3_driver_data->gicd_base, in gicv3_distif_init()
211 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); in gicv3_distif_init()
214 gicv3_driver_data->gicd_base, in gicv3_distif_init()
219 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); in gicv3_distif_init()
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| H A D | gicv3_helpers.c | 22 uintptr_t gicv3_get_multichip_base(uint32_t spi_id, uintptr_t gicd_base) in gicv3_get_multichip_base() argument
29 return gicd_base; in gicv3_get_multichip_base()
121 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base) in gicv3_get_spi_limit() argument
124 unsigned int typer_reg = gicd_read_typer(gicd_base); in gicv3_get_spi_limit()
141 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base) in gicv3_get_espi_limit() argument
143 unsigned int typer_reg = gicd_read_typer(gicd_base); in gicv3_get_espi_limit()
162 void gicv3_spis_config_defaults(uintptr_t gicd_base) in gicv3_spis_config_defaults() argument
169 num_ints = gicv3_get_spi_limit(gicd_base); in gicv3_spis_config_defaults()
174 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); in gicv3_spis_config_defaults()
178 num_eints = gicv3_get_espi_limit(gicd_base); in gicv3_spis_config_defaults()
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| H A D | arm_gicv3_common.c | 35 assert(gicv3_driver_data->gicd_base != 0U); in arm_gicv3_distif_pre_save()
37 typer_reg = gicd_read_typer(gicv3_driver_data->gicd_base); in arm_gicv3_distif_pre_save()
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| H A D | gic-x00.c | 198 void gicv3_check_erratas_applies(const uintptr_t gicd_base) in gicv3_check_erratas_applies() argument
203 assert(gicd_base != 0UL); in gicv3_check_erratas_applies()
205 gicv3_get_component_prodid_rev(gicd_base, &gic_prod_id, &gic_rev); in gicv3_check_erratas_applies()
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| /rk3399_ARM-atf/drivers/arm/gic/v2/ |
| H A D | gicv2_helpers.c | 93 void gicv2_spis_configure_defaults(uintptr_t gicd_base) in gicv2_spis_configure_defaults() argument
97 num_ints = gicd_read_typer(gicd_base); in gicv2_spis_configure_defaults()
106 gicd_write_igroupr(gicd_base, index, ~0U); in gicv2_spis_configure_defaults()
110 gicd_write_ipriorityr(gicd_base, in gicv2_spis_configure_defaults()
116 gicd_write_icfgr(gicd_base, index, 0U); in gicv2_spis_configure_defaults()
123 void gicv2_secure_spis_configure_props(uintptr_t gicd_base, in gicv2_secure_spis_configure_props() argument
142 gicd_clr_igroupr(gicd_base, prop_desc->intr_num); in gicv2_secure_spis_configure_props()
145 gicd_set_ipriorityr(gicd_base, prop_desc->intr_num, in gicv2_secure_spis_configure_props()
149 gicd_set_itargetsr(gicd_base, prop_desc->intr_num, in gicv2_secure_spis_configure_props()
150 gicv2_get_cpuif_id(gicd_base)); in gicv2_secure_spis_configure_props()
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| H A D | gicv2_main.c | 82 assert(driver_data->gicd_base != 0U); in gicv2_pcpu_distif_init()
84 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, in gicv2_pcpu_distif_init()
89 ctlr = gicd_read_ctlr(driver_data->gicd_base); in gicv2_pcpu_distif_init()
91 gicd_write_ctlr(driver_data->gicd_base, in gicv2_pcpu_distif_init()
106 assert(driver_data->gicd_base != 0U); in gicv2_distif_init()
109 ctlr = gicd_read_ctlr(driver_data->gicd_base); in gicv2_distif_init()
110 gicd_write_ctlr(driver_data->gicd_base, in gicv2_distif_init()
114 gicv2_spis_configure_defaults(driver_data->gicd_base); in gicv2_distif_init()
116 gicv2_secure_spis_configure_props(driver_data->gicd_base, in gicv2_distif_init()
122 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); in gicv2_distif_init()
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| H A D | gicv2_private.h | 18 void gicv2_spis_configure_defaults(uintptr_t gicd_base);
19 void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
22 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
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| H A D | gicv2_base.c | 30 .gicd_base = PLAT_ARM_GICD_BASE,
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| /rk3399_ARM-atf/plat/qemu/qemu_sbsa/ |
| H A D | sbsa_gic.c | 24 .gicd_base = GICD_BASE,
33 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base) in sbsa_set_gic_bases() argument
35 sbsa_gic_driver_data.gicd_base = gicd_base; in sbsa_set_gic_bases()
41 return sbsa_gic_driver_data.gicd_base; in sbsa_get_gicd()
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| H A D | sbsa_platform.c | 23 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
213 uintptr_t gicd_base; in read_platform_config_from_dt() local
237 err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL); in read_platform_config_from_dt()
242 INFO("GICD base = 0x%lx\n", gicd_base); in read_platform_config_from_dt()
251 sbsa_set_gic_bases(gicd_base, gicr_base); in read_platform_config_from_dt()
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| /rk3399_ARM-atf/plat/nxp/soc-ls1043a/ |
| H A D | soc.c | 360 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) in get_gic_offset() argument
373 *gicd_base = NXP_GICD_4K_ADDR; in get_gic_offset()
376 *gicd_base = NXP_GICD_64K_ADDR; in get_gic_offset()
380 *gicd_base = NXP_GICD_4K_ADDR; in get_gic_offset()
396 static uint32_t gicc_base, gicd_base; in soc_platform_setup() local
398 get_gic_offset(&gicc_base, &gicd_base); in soc_platform_setup()
399 plat_ls_gic_driver_init(gicd_base, gicc_base, in soc_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_gicv3.c | 76 gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config, in fvp_gic_driver_pre_init()
78 gicd_base); in fvp_gic_driver_pre_init()
91 gic_data.gicd_base = PLAT_ARM_GICD_BASE; in fvp_gic_driver_pre_init()
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| /rk3399_ARM-atf/plat/ti/common/ |
| H A D | k3_gicv3.c | 46 uintptr_t gicd_base = gic_base; in k3_gic_driver_init() local
68 k3_gic_data.gicd_base = gicd_base; in k3_gic_driver_init()
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| /rk3399_ARM-atf/plat/socionext/uniphier/ |
| H A D | uniphier_gicv3.c | 61 .gicd_base = 0x5fe00000,
70 .gicd_base = 0x5fe00000,
79 .gicd_base = 0x5fe00000,
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| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/ |
| H A D | plat_bl31_setup.c | 60 ret = mmap_add_dynamic_region(gic_data->gicd_base, in mmap_gic()
61 gic_data->gicd_base, in mmap_gic()
84 .gicd_base = PLAT_GICD_BASE, in bl31_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/arm_fpga/ |
| H A D | fpga_gicv3.c | 55 &fpga_gicv3_driver_data.gicd_base, NULL); in plat_fpga_gic_init()
61 iidr = mmio_read_32(fpga_gicv3_driver_data.gicd_base + GICD_IIDR); in plat_fpga_gic_init()
71 gicr_base = fpga_gicv3_driver_data.gicd_base + (4U << 16); in plat_fpga_gic_init()
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| /rk3399_ARM-atf/plat/qemu/common/ |
| H A D | qemu_gicv2.c | 17 .gicd_base = GICD_BASE,
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| H A D | qemu_gicv3.c | 25 .gicd_base = GICD_BASE,
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| /rk3399_ARM-atf/plat/nuvoton/common/ |
| H A D | plat_nuvoton_gic.c | 20 .gicd_base = BASE_GICD_BASE,
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| /rk3399_ARM-atf/include/drivers/arm/ |
| H A D | gic600_multichip.h | 20 uintptr_t gicd_base; member
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| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | rockchip_gicv2.c | 37 .gicd_base = PLAT_RK_GICD_BASE,
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| /rk3399_ARM-atf/plat/hisilicon/poplar/ |
| H A D | poplar_gicv2.c | 24 .gicd_base = POPLAR_GICD_BASE,
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| /rk3399_ARM-atf/plat/nvidia/tegra/common/ |
| H A D | tegra_gicv2.c | 35 tegra_gic_data.gicd_base = TEGRA_GICD_BASE; in tegra_gic_setup()
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| /rk3399_ARM-atf/plat/arm/board/fvp/fconf/ |
| H A D | fconf_gicv3_config_getter.c | 43 gicv3_config.gicd_base = addr; in fconf_populate_gicv3_config()
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| /rk3399_ARM-atf/drivers/nxp/gic/ |
| H A D | ls_gicv2.c | 24 ls_gic_data.gicd_base = nxp_gicd_addr; in plat_ls_gic_driver_init()
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